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llvm-6502/test/MC
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Mihai Popa 5f268555b9 Fix ARM vcvt encoding when the number of fractional bits is zero. 
The instruction to convert between floating point and fixed point representations
takes an immediate operand for the number of fractional bits of the fixed point
value. ARMARM specifies that when that number of bits is zero, the assembler
should encode floating point/integer conversion instructions. 

This patch adds the necessary instruction aliases to achieve this behaviour.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 13:16:07 +00:00
..
AArch64 [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00
ARM Fix ARM vcvt encoding when the number of fractional bits is zero. 2013-08-22 13:16:07 +00:00
AsmParser [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00
COFF [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00
Disassembler [SystemZ] Add FI[EDX]BRA 2013-08-21 08:58:08 +00:00
ELF [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00
MachO [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00
Markup
Mips [micromips] Print instruction alias "not" if the last operand of a nor is zero. 2013-08-21 01:18:46 +00:00
PowerPC Add the PPC fcpsgn instruction 2013-08-19 05:01:02 +00:00
SystemZ [SystemZ] Add FI[EDX]BRA 2013-08-21 08:58:08 +00:00
X86 AVX-512: Added SHIFT instructions. 2013-08-21 09:36:02 +00:00