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https://github.com/c64scene-ar/llvm-6502.git
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2a9d1ca9c2
The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.8 KiB
TableGen
57 lines
1.8 KiB
TableGen
//===- XCoreRegisterInfo.td - XCore Register defs ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the XCore register file
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//===----------------------------------------------------------------------===//
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class XCoreReg<string n> : Register<n> {
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field bits<4> Num;
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let Namespace = "XCore";
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}
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// Registers are identified with 4-bit ID numbers.
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// Ri - 32-bit integer registers
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class Ri<bits<4> num, string n> : XCoreReg<n> {
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let Num = num;
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}
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// CPU registers
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def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
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def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
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def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
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def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
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def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
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def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
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def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
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def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
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def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
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def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
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def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
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def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
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def CP : Ri<12, "cp">, DwarfRegNum<[12]>;
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def DP : Ri<13, "dp">, DwarfRegNum<[13]>;
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def SP : Ri<14, "sp">, DwarfRegNum<[14]>;
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def LR : Ri<15, "lr">, DwarfRegNum<[15]>;
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// Register classes.
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//
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def GRRegs : RegisterClass<"XCore", [i32], 32,
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// Return values and arguments
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[R0, R1, R2, R3,
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// Not preserved across procedure calls
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R11,
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// Callee save
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R4, R5, R6, R7, R8, R9, R10]>;
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// Reserved
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def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> {
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let isAllocatable = 0;
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}
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