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5de728cfe1
This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
13 lines
446 B
ArmAsm
13 lines
446 B
ArmAsm
// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
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// RUN: FileCheck --check-prefix=64 < %t.err %s
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// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
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// RUN: FileCheck --check-prefix=32 < %t.err %s
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// rdar://8204588
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// 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
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cmp $0, 0(%eax)
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// 32: error: register %rax is only available in 64-bit mode
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addl $0, 0(%rax)
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