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https://github.com/c64scene-ar/llvm-6502.git
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There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
350 lines
13 KiB
C++
350 lines
13 KiB
C++
//==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAGInstrs class, which implements
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// scheduling for a MachineInstr-based dependency graph.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SCHEDULEDAGINSTRS_H
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#define SCHEDULEDAGINSTRS_H
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SparseSet.h"
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#include <map>
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namespace llvm {
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class MachineLoopInfo;
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class MachineDominatorTree;
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class LiveIntervals;
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class RegPressureTracker;
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/// LoopDependencies - This class analyzes loop-oriented register
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/// dependencies, which are used to guide scheduling decisions.
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/// For example, loop induction variable increments should be
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/// scheduled as soon as possible after the variable's last use.
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///
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class LoopDependencies {
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const MachineDominatorTree &MDT;
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public:
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typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
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LoopDeps;
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LoopDeps Deps;
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LoopDependencies(const MachineDominatorTree &mdt) : MDT(mdt) {}
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/// VisitLoop - Clear out any previous state and analyze the given loop.
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///
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void VisitLoop(const MachineLoop *Loop) {
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assert(Deps.empty() && "stale loop dependencies");
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MachineBasicBlock *Header = Loop->getHeader();
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SmallSet<unsigned, 8> LoopLiveIns;
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for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
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LE = Header->livein_end(); LI != LE; ++LI)
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LoopLiveIns.insert(*LI);
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const MachineDomTreeNode *Node = MDT.getNode(Header);
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const MachineBasicBlock *MBB = Node->getBlock();
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assert(Loop->contains(MBB) &&
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"Loop does not contain header!");
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VisitRegion(Node, MBB, Loop, LoopLiveIns);
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}
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private:
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void VisitRegion(const MachineDomTreeNode *Node,
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const MachineBasicBlock *MBB,
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const MachineLoop *Loop,
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const SmallSet<unsigned, 8> &LoopLiveIns) {
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unsigned Count = 0;
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for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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const MachineInstr *MI = I;
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if (MI->isDebugValue())
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continue;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned MOReg = MO.getReg();
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if (LoopLiveIns.count(MOReg))
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Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
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}
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++Count; // Not every iteration due to dbg_value above.
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}
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const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
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for (std::vector<MachineDomTreeNode*>::const_iterator I =
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Children.begin(), E = Children.end(); I != E; ++I) {
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const MachineDomTreeNode *ChildNode = *I;
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MachineBasicBlock *ChildBlock = ChildNode->getBlock();
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if (Loop->contains(ChildBlock))
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VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
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}
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}
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};
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/// An individual mapping from virtual register number to SUnit.
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struct VReg2SUnit {
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unsigned VirtReg;
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SUnit *SU;
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VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
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unsigned getSparseSetIndex() const {
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return TargetRegisterInfo::virtReg2Index(VirtReg);
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}
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};
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/// Combine a SparseSet with a 1x1 vector to track physical registers.
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/// The SparseSet allows iterating over the (few) live registers for quickly
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/// comparing against a regmask or clearing the set.
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///
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/// Storage for the map is allocated once for the pass. The map can be
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/// cleared between scheduling regions without freeing unused entries.
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class Reg2SUnitsMap {
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SparseSet<unsigned> PhysRegSet;
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std::vector<std::vector<SUnit*> > SUnits;
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public:
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typedef SparseSet<unsigned>::const_iterator const_iterator;
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// Allow iteration over register numbers (keys) in the map. If needed, we
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// can provide an iterator over SUnits (values) as well.
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const_iterator reg_begin() const { return PhysRegSet.begin(); }
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const_iterator reg_end() const { return PhysRegSet.end(); }
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/// Initialize the map with the number of registers.
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/// If the map is already large enough, no allocation occurs.
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/// For simplicity we expect the map to be empty().
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void setRegLimit(unsigned Limit);
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/// Returns true if the map is empty.
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bool empty() const { return PhysRegSet.empty(); }
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/// Clear the map without deallocating storage.
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void clear();
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bool contains(unsigned Reg) const { return PhysRegSet.count(Reg); }
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/// If this register is mapped, return its existing SUnits vector.
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/// Otherwise map the register and return an empty SUnits vector.
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std::vector<SUnit *> &operator[](unsigned Reg) {
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bool New = PhysRegSet.insert(Reg).second;
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assert((!New || SUnits[Reg].empty()) && "stale SUnits vector");
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(void)New;
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return SUnits[Reg];
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}
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/// Erase an existing element without freeing memory.
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void erase(unsigned Reg) {
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PhysRegSet.erase(Reg);
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SUnits[Reg].clear();
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}
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};
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/// Use SparseSet as a SparseMap by relying on the fact that it never
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/// compares ValueT's, only unsigned keys. This allows the set to be cleared
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/// between scheduling regions in constant time as long as ValueT does not
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/// require a destructor.
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typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
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/// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
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/// MachineInstrs.
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class ScheduleDAGInstrs : public ScheduleDAG {
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protected:
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const MachineLoopInfo &MLI;
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const MachineDominatorTree &MDT;
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const MachineFrameInfo *MFI;
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const InstrItineraryData *InstrItins;
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/// Live Intervals provides reaching defs in preRA scheduling.
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LiveIntervals *LIS;
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/// isPostRA flag indicates vregs cannot be present.
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bool IsPostRA;
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/// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
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/// the def-side latency only.
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bool UnitLatencies;
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/// The standard DAG builder does not normally include terminators as DAG
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/// nodes because it does not create the necessary dependencies to prevent
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/// reordering. A specialized scheduler can overide
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/// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
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/// it has taken responsibility for scheduling the terminator correctly.
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bool CanHandleTerminators;
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/// State specific to the current scheduling region.
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/// ------------------------------------------------
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/// The block in which to insert instructions
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MachineBasicBlock *BB;
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/// The beginning of the range to be scheduled.
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MachineBasicBlock::iterator RegionBegin;
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/// The end of the range to be scheduled.
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MachineBasicBlock::iterator RegionEnd;
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/// The index in BB of RegionEnd.
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unsigned EndIndex;
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/// After calling BuildSchedGraph, each machine instruction in the current
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/// scheduling region is mapped to an SUnit.
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DenseMap<MachineInstr*, SUnit*> MISUnitMap;
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/// State internal to DAG building.
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/// -------------------------------
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/// Defs, Uses - Remember where defs and uses of each register are as we
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/// iterate upward through the instructions. This is allocated here instead
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/// of inside BuildSchedGraph to avoid the need for it to be initialized and
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/// destructed for each block.
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Reg2SUnitsMap Defs;
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Reg2SUnitsMap Uses;
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/// Track the last instructon in this region defining each virtual register.
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VReg2SUnitMap VRegDefs;
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/// PendingLoads - Remember where unknown loads are after the most recent
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/// unknown store, as we iterate. As with Defs and Uses, this is here
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/// to minimize construction/destruction.
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std::vector<SUnit *> PendingLoads;
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/// LoopRegs - Track which registers are used for loop-carried dependencies.
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///
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LoopDependencies LoopRegs;
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/// DbgValues - Remember instruction that precedes DBG_VALUE.
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/// These are generated by buildSchedGraph but persist so they can be
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/// referenced when emitting the final schedule.
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typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
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DbgValueVector;
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DbgValueVector DbgValues;
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MachineInstr *FirstDbgValue;
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public:
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explicit ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt,
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bool IsPostRAFlag,
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LiveIntervals *LIS = 0);
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virtual ~ScheduleDAGInstrs() {}
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/// begin - Return an iterator to the top of the current scheduling region.
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MachineBasicBlock::iterator begin() const { return RegionBegin; }
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/// end - Return an iterator to the bottom of the current scheduling region.
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MachineBasicBlock::iterator end() const { return RegionEnd; }
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/// newSUnit - Creates a new SUnit and return a ptr to it.
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SUnit *newSUnit(MachineInstr *MI);
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/// getSUnit - Return an existing SUnit for this MI, or NULL.
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SUnit *getSUnit(MachineInstr *MI) const;
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/// startBlock - Prepare to perform scheduling in the given block.
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virtual void startBlock(MachineBasicBlock *BB);
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/// finishBlock - Clean up after scheduling in the given block.
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virtual void finishBlock();
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/// Initialize the scheduler state for the next scheduling region.
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virtual void enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned endcount);
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/// Notify that the scheduler has finished scheduling the current region.
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virtual void exitRegion();
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/// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
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/// input.
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void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0);
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/// addSchedBarrierDeps - Add dependencies from instructions in the current
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/// list of instructions being scheduled to scheduling barrier. We want to
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/// make sure instructions which define registers that are either used by
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/// the terminator or are live-out are properly scheduled. This is
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/// especially important when the definition latency of the return value(s)
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/// are too high to be hidden by the branch or when the liveout registers
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/// used by instructions in the fallthrough block.
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void addSchedBarrierDeps();
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/// computeLatency - Compute node latency.
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///
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virtual void computeLatency(SUnit *SU);
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/// computeOperandLatency - Return dependence edge latency using
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/// operand use/def information
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///
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/// FindMin may be set to get the minimum vs. expected latency. Minimum
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/// latency is used for scheduling groups, while expected latency is for
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/// instruction cost and critical path.
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virtual unsigned computeOperandLatency(SUnit *Def, SUnit *Use,
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const SDep& dep,
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bool FindMin = false) const;
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/// schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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///
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/// Typically, a scheduling algorithm will implement schedule() without
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/// overriding enterRegion() or exitRegion().
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virtual void schedule() = 0;
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/// finalizeSchedule - Allow targets to perform final scheduling actions at
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/// the level of the whole MachineFunction. By default does nothing.
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virtual void finalizeSchedule() {}
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virtual void dumpNode(const SUnit *SU) const;
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/// Return a label for a DAG node that points to an instruction.
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virtual std::string getGraphNodeLabel(const SUnit *SU) const;
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/// Return a label for the region of code covered by the DAG.
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virtual std::string getDAGName() const;
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protected:
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void initSUnits();
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void addPhysRegDataDeps(SUnit *SU, const MachineOperand &MO);
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void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
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void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
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void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
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};
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/// newSUnit - Creates a new SUnit and return a ptr to it.
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inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
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#ifndef NDEBUG
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const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
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#endif
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SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
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assert((Addr == 0 || Addr == &SUnits[0]) &&
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"SUnits std::vector reallocated on the fly!");
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SUnits.back().OrigNode = &SUnits.back();
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return &SUnits.back();
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}
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/// getSUnit - Return an existing SUnit for this MI, or NULL.
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inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
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DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
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if (I == MISUnitMap.end())
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return 0;
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return I->second;
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}
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} // namespace llvm
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#endif
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