mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b503b49b51
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
254 lines
6.7 KiB
LLVM
254 lines
6.7 KiB
LLVM
; Test 64-bit comparison in which the second operand is a zero-extended i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check unsigned register comparison.
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define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
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; CHECK: f1:
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; CHECK: clgfr %r2, %r3
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; CHECK-NEXT: j{{g?}}l
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%i2 = zext i32 %unext to i64
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%cond = icmp ult i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; ...and again with a different representation.
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define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
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; CHECK: f2:
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; CHECK: clgfr %r2, %r3
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; CHECK-NEXT: j{{g?}}l
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%i2 = and i64 %unext, 4294967295
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%cond = icmp ult i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check signed register comparison, which can't use CLGFR.
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define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
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; CHECK: f3:
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; CHECK-NOT: clgfr
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; CHECK: br %r14
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%i2 = zext i32 %unext to i64
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%cond = icmp slt i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; ...and again with a different representation
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define double @f4(double %a, double %b, i64 %i1, i64 %unext) {
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; CHECK: f4:
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; CHECK-NOT: clgfr
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; CHECK: br %r14
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%i2 = and i64 %unext, 4294967295
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%cond = icmp slt i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check register equality.
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define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
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; CHECK: f5:
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; CHECK: clgfr %r2, %r3
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; CHECK-NEXT: j{{g?}}e
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%i2 = zext i32 %unext to i64
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%cond = icmp eq i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; ...and again with a different representation
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define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
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; CHECK: f6:
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; CHECK: clgfr %r2, %r3
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; CHECK-NEXT: j{{g?}}e
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%i2 = and i64 %unext, 4294967295
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%cond = icmp eq i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check register inequality.
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define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
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; CHECK: f7:
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; CHECK: clgfr %r2, %r3
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; CHECK-NEXT: j{{g?}}lh
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%i2 = zext i32 %unext to i64
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%cond = icmp ne i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; ...and again with a different representation
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define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
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; CHECK: f8:
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; CHECK: clgfr %r2, %r3
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; CHECK-NEXT: j{{g?}}lh
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%i2 = and i64 %unext, 4294967295
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%cond = icmp ne i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check unsigned comparisonn with memory.
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define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
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; CHECK: f9:
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; CHECK: clgf %r2, 0(%r3)
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; CHECK-NEXT: j{{g?}}l
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp ult i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check signed comparison with memory.
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define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) {
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; CHECK: f10:
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; CHECK-NOT: clgf
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; CHECK: br %r14
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp slt i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check memory equality.
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define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
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; CHECK: f11:
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; CHECK: clgf %r2, 0(%r3)
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; CHECK-NEXT: j{{g?}}e
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp eq i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check memory inequality.
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define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
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; CHECK: f12:
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; CHECK: clgf %r2, 0(%r3)
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; CHECK-NEXT: j{{g?}}lh
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp ne i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the high end of the aligned CLGF range.
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define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
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; CHECK: f13:
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; CHECK: clgf %r2, 524284(%r3)
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; CHECK-NEXT: j{{g?}}l
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 131071
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp ult i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
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; CHECK: f14:
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; CHECK: agfi %r3, 524288
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; CHECK: clgf %r2, 0(%r3)
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; CHECK-NEXT: j{{g?}}l
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 131072
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp ult i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the high end of the negative aligned CLGF range.
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define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
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; CHECK: f15:
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; CHECK: clgf %r2, -4(%r3)
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; CHECK-NEXT: j{{g?}}l
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -1
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp ult i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the low end of the CLGF range.
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define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
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; CHECK: f16:
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; CHECK: clgf %r2, -524288(%r3)
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; CHECK-NEXT: j{{g?}}l
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -131072
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp ult i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
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; CHECK: f17:
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; CHECK: agfi %r3, -524292
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; CHECK: clgf %r2, 0(%r3)
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; CHECK-NEXT: j{{g?}}l
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -131073
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp ult i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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; Check that CLGF allows an index.
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define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
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; CHECK: f18:
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; CHECK: clgf %r2, 524284({{%r4,%r3|%r3,%r4}})
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; CHECK-NEXT: j{{g?}}l
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 524284
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%ptr = inttoptr i64 %add2 to i32 *
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%unext = load i32 *%ptr
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%i2 = zext i32 %unext to i64
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%cond = icmp ult i64 %i1, %i2
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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