llvm-6502/lib/Target/Alpha
Dan Gohman 8be6bbe5bf Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05 04:14:16 +00:00
..
Alpha.h Use raw_ostream throughout the AsmPrinter. 2008-08-21 00:14:44 +00:00
Alpha.td
AlphaAsmPrinter.cpp Switch the MachineOperand accessors back to the short names like 2008-10-03 15:45:36 +00:00
AlphaBranchSelector.cpp Tidy up several unbeseeming casts from pointer to intptr_t. 2008-09-04 17:05:41 +00:00
AlphaCodeEmitter.cpp Switch the MachineOperand accessors back to the short names like 2008-10-03 15:45:36 +00:00
AlphaInstrFormats.td
AlphaInstrInfo.cpp Const-ify several TargetInstrInfo methods. 2008-10-16 01:49:15 +00:00
AlphaInstrInfo.h Const-ify several TargetInstrInfo methods. 2008-10-16 01:49:15 +00:00
AlphaInstrInfo.td Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as 2008-10-11 22:08:30 +00:00
AlphaISelDAGToDAG.cpp Eliminate the ISel priority queue, which used the topological order for a 2008-11-05 04:14:16 +00:00
AlphaISelLowering.cpp Teach DAGCombine to fold constant offsets into GlobalAddress nodes, 2008-10-18 02:06:02 +00:00
AlphaISelLowering.h Teach DAGCombine to fold constant offsets into GlobalAddress nodes, 2008-10-18 02:06:02 +00:00
AlphaJITInfo.cpp
AlphaJITInfo.h Trim #includes. 2008-08-05 15:32:23 +00:00
AlphaLLRP.cpp Tidy up several unbeseeming casts from pointer to intptr_t. 2008-09-04 17:05:41 +00:00
AlphaRegisterInfo.cpp Switch the MachineOperand accessors back to the short names like 2008-10-03 15:45:36 +00:00
AlphaRegisterInfo.h
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetAsmInfo.cpp Refactor various TargetAsmInfo subclasses' TargetMachine members away 2008-11-03 18:22:42 +00:00
AlphaTargetAsmInfo.h
AlphaTargetMachine.cpp mark some targets as experimental. Andrew, if you think that Alpha is 2008-10-16 06:16:50 +00:00
AlphaTargetMachine.h Use raw_ostream throughout the AsmPrinter. 2008-08-21 00:14:44 +00:00
CMakeLists.txt CMake: Builds all targets. 2008-09-26 04:40:32 +00:00
Makefile
README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html