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enabled by passing -tailcallopt to llc. The optimization is performed if the following conditions are satisfied: * caller/callee are fastcc * elf/pic is disabled OR elf/pic enabled + callee is in module + callee has visibility protected or hidden git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42870 91177308-0d34-0410-b5e6-96231b3b80d8
740 lines
27 KiB
C++
740 lines
27 KiB
C++
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstrInfo.h"
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#include "X86.h"
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#include "X86GenInstrInfo.inc"
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#include "X86InstrBuilder.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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: TargetInstrInfo(X86Insts, array_lengthof(X86Insts)),
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TM(tm), RI(tm, *this) {
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}
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bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
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oc == X86::MOV32rr || oc == X86::MOV64rr ||
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oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
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oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
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oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 ||
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oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
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oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
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oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
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oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
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oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid register-register move instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case X86::MOV8rm:
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case X86::MOV16rm:
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case X86::MOV16_rm:
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case X86::MOV32rm:
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case X86::MOV32_rm:
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case X86::MOV64rm:
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case X86::LD_Fp64m:
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case X86::MOVSSrm:
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case X86::MOVSDrm:
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case X86::MOVAPSrm:
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case X86::MOVAPDrm:
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case X86::MMX_MOVD64rm:
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case X86::MMX_MOVQ64rm:
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if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
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MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 1 &&
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MI->getOperand(3).getReg() == 0 &&
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MI->getOperand(4).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case X86::MOV8mr:
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case X86::MOV16mr:
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case X86::MOV16_mr:
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case X86::MOV32mr:
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case X86::MOV32_mr:
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case X86::MOV64mr:
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case X86::ST_FpP64m:
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case X86::MOVSSmr:
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case X86::MOVSDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDmr:
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case X86::MMX_MOVD64mr:
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case X86::MMX_MOVQ64mr:
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case X86::MMX_MOVNTQmr:
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if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
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MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
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MI->getOperand(1).getImmedValue() == 1 &&
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MI->getOperand(2).getReg() == 0 &&
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MI->getOperand(3).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(0).getFrameIndex();
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return MI->getOperand(4).getReg();
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}
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break;
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}
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return 0;
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}
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bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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default: break;
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case X86::MOV8rm:
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case X86::MOV16rm:
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case X86::MOV16_rm:
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case X86::MOV32rm:
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case X86::MOV32_rm:
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case X86::MOV64rm:
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case X86::LD_Fp64m:
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case X86::MOVSSrm:
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case X86::MOVSDrm:
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case X86::MOVAPSrm:
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case X86::MOVAPDrm:
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case X86::MMX_MOVD64rm:
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case X86::MMX_MOVQ64rm:
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// Loads from constant pools are trivially rematerializable.
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return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
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MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
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MI->getOperand(1).getReg() == 0 &&
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MI->getOperand(2).getImmedValue() == 1 &&
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MI->getOperand(3).getReg() == 0;
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}
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// All other instructions marked M_REMATERIALIZABLE are always trivially
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// rematerializable.
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return true;
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}
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/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
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/// is not marked dead.
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static bool hasLiveCondCodeDef(MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDef() &&
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MO.getReg() == X86::EFLAGS && !MO.isDead()) {
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return true;
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}
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}
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return false;
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}
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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MachineInstr *
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X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables &LV) const {
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MachineInstr *MI = MBBI;
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// All instructions input are two-addr instructions. Get the known operands.
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Src = MI->getOperand(1).getReg();
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MachineInstr *NewMI = NULL;
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// FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
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// we have better subtarget support, enable the 16-bit LEA generation here.
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bool DisableLEA16 = true;
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unsigned MIOpc = MI->getOpcode();
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switch (MIOpc) {
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case X86::SHUFPSrri: {
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assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
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if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
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unsigned A = MI->getOperand(0).getReg();
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unsigned B = MI->getOperand(1).getReg();
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unsigned C = MI->getOperand(2).getReg();
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unsigned M = MI->getOperand(3).getImm();
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if (B != C) return 0;
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NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
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break;
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}
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case X86::SHL64ri: {
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assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
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// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
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// the flags produced by a shift yet, so this is safe.
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Src = MI->getOperand(1).getReg();
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unsigned ShAmt = MI->getOperand(2).getImm();
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if (ShAmt == 0 || ShAmt >= 4) return 0;
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NewMI = BuildMI(get(X86::LEA64r), Dest)
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.addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
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break;
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}
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case X86::SHL32ri: {
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assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
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// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
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// the flags produced by a shift yet, so this is safe.
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Src = MI->getOperand(1).getReg();
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unsigned ShAmt = MI->getOperand(2).getImm();
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if (ShAmt == 0 || ShAmt >= 4) return 0;
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unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
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X86::LEA64_32r : X86::LEA32r;
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NewMI = BuildMI(get(Opc), Dest)
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.addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
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break;
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}
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case X86::SHL16ri: {
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assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
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// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
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// the flags produced by a shift yet, so this is safe.
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unsigned Dest = MI->getOperand(0).getReg();
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unsigned Src = MI->getOperand(1).getReg();
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unsigned ShAmt = MI->getOperand(2).getImm();
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if (ShAmt == 0 || ShAmt >= 4) return 0;
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if (DisableLEA16) {
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// If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
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SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
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unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
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? X86::LEA64_32r : X86::LEA32r;
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unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
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unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
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MachineInstr *Ins =
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BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
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Ins->copyKillDeadInfo(MI);
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NewMI = BuildMI(get(Opc), leaOutReg)
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.addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
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MachineInstr *Ext =
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BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
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Ext->copyKillDeadInfo(MI);
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MFI->insert(MBBI, Ins); // Insert the insert_subreg
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LV.instructionChanged(MI, NewMI); // Update live variables
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LV.addVirtualRegisterKilled(leaInReg, NewMI);
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MFI->insert(MBBI, NewMI); // Insert the new inst
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LV.addVirtualRegisterKilled(leaOutReg, Ext);
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MFI->insert(MBBI, Ext); // Insert the extract_subreg
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return Ext;
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} else {
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NewMI = BuildMI(get(X86::LEA16r), Dest)
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.addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
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}
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break;
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}
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default: {
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// The following opcodes also sets the condition code register(s). Only
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// convert them to equivalent lea if the condition code register def's
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// are dead!
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if (hasLiveCondCodeDef(MI))
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return 0;
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bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
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switch (MIOpc) {
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default: return 0;
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case X86::INC64r:
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case X86::INC32r: {
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assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
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unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
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: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
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NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
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break;
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}
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case X86::INC16r:
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case X86::INC64_16r:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
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NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
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break;
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case X86::DEC64r:
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case X86::DEC32r: {
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assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
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unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
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: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
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NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
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break;
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}
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case X86::DEC16r:
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case X86::DEC64_16r:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
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NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
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break;
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case X86::ADD64rr:
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case X86::ADD32rr: {
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
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: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
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NewMI = addRegReg(BuildMI(get(Opc), Dest), Src,
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MI->getOperand(2).getReg());
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break;
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}
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case X86::ADD16rr:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
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MI->getOperand(2).getReg());
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break;
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case X86::ADD64ri32:
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case X86::ADD64ri8:
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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if (MI->getOperand(2).isImmediate())
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NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
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MI->getOperand(2).getImmedValue());
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break;
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case X86::ADD32ri:
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case X86::ADD32ri8:
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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if (MI->getOperand(2).isImmediate()) {
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unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
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NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
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MI->getOperand(2).getImmedValue());
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}
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break;
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case X86::ADD16ri:
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case X86::ADD16ri8:
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if (DisableLEA16) return 0;
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assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
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if (MI->getOperand(2).isImmediate())
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NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
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MI->getOperand(2).getImmedValue());
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break;
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case X86::SHL16ri:
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if (DisableLEA16) return 0;
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case X86::SHL32ri:
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case X86::SHL64ri: {
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assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
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"Unknown shl instruction!");
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unsigned ShAmt = MI->getOperand(2).getImmedValue();
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if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
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X86AddressMode AM;
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AM.Scale = 1 << ShAmt;
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AM.IndexReg = Src;
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unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
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: (MIOpc == X86::SHL32ri
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? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
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NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
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}
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break;
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}
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}
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}
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}
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NewMI->copyKillDeadInfo(MI);
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LV.instructionChanged(MI, NewMI); // Update live variables
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MFI->insert(MBBI, NewMI); // Insert the new inst
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return NewMI;
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}
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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///
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MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
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case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
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case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
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case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
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case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
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case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
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unsigned Opc;
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unsigned Size;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unreachable!");
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case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
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case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
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case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
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case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
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case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
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case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
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}
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unsigned Amt = MI->getOperand(3).getImmedValue();
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unsigned A = MI->getOperand(0).getReg();
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unsigned B = MI->getOperand(1).getReg();
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unsigned C = MI->getOperand(2).getReg();
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bool BisKill = MI->getOperand(1).isKill();
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bool CisKill = MI->getOperand(2).isKill();
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return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
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.addReg(B, false, false, BisKill).addImm(Size-Amt);
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}
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case X86::CMOVB16rr:
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case X86::CMOVB32rr:
|
|
case X86::CMOVB64rr:
|
|
case X86::CMOVAE16rr:
|
|
case X86::CMOVAE32rr:
|
|
case X86::CMOVAE64rr:
|
|
case X86::CMOVE16rr:
|
|
case X86::CMOVE32rr:
|
|
case X86::CMOVE64rr:
|
|
case X86::CMOVNE16rr:
|
|
case X86::CMOVNE32rr:
|
|
case X86::CMOVNE64rr:
|
|
case X86::CMOVBE16rr:
|
|
case X86::CMOVBE32rr:
|
|
case X86::CMOVBE64rr:
|
|
case X86::CMOVA16rr:
|
|
case X86::CMOVA32rr:
|
|
case X86::CMOVA64rr:
|
|
case X86::CMOVL16rr:
|
|
case X86::CMOVL32rr:
|
|
case X86::CMOVL64rr:
|
|
case X86::CMOVGE16rr:
|
|
case X86::CMOVGE32rr:
|
|
case X86::CMOVGE64rr:
|
|
case X86::CMOVLE16rr:
|
|
case X86::CMOVLE32rr:
|
|
case X86::CMOVLE64rr:
|
|
case X86::CMOVG16rr:
|
|
case X86::CMOVG32rr:
|
|
case X86::CMOVG64rr:
|
|
case X86::CMOVS16rr:
|
|
case X86::CMOVS32rr:
|
|
case X86::CMOVS64rr:
|
|
case X86::CMOVNS16rr:
|
|
case X86::CMOVNS32rr:
|
|
case X86::CMOVNS64rr:
|
|
case X86::CMOVP16rr:
|
|
case X86::CMOVP32rr:
|
|
case X86::CMOVP64rr:
|
|
case X86::CMOVNP16rr:
|
|
case X86::CMOVNP32rr:
|
|
case X86::CMOVNP64rr: {
|
|
unsigned Opc = 0;
|
|
switch (MI->getOpcode()) {
|
|
default: break;
|
|
case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
|
|
case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
|
|
case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
|
|
case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
|
|
case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
|
|
case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
|
|
case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
|
|
case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
|
|
case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
|
|
case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
|
|
case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
|
|
case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
|
|
case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
|
|
case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
|
|
case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
|
|
case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
|
|
case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
|
|
case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
|
|
case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
|
|
case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
|
|
case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
|
|
case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
|
|
case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
|
|
case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
|
|
case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
|
|
case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
|
|
case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
|
|
case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
|
|
case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
|
|
case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
|
|
case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
|
|
case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
|
|
case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
|
|
case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
|
|
case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
|
|
case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
|
|
case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
|
|
case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
|
|
case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
|
|
case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
|
|
case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
|
|
case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
|
|
}
|
|
|
|
MI->setInstrDescriptor(get(Opc));
|
|
// Fallthrough intended.
|
|
}
|
|
default:
|
|
return TargetInstrInfo::commuteInstruction(MI);
|
|
}
|
|
}
|
|
|
|
static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
|
|
switch (BrOpc) {
|
|
default: return X86::COND_INVALID;
|
|
case X86::JE: return X86::COND_E;
|
|
case X86::JNE: return X86::COND_NE;
|
|
case X86::JL: return X86::COND_L;
|
|
case X86::JLE: return X86::COND_LE;
|
|
case X86::JG: return X86::COND_G;
|
|
case X86::JGE: return X86::COND_GE;
|
|
case X86::JB: return X86::COND_B;
|
|
case X86::JBE: return X86::COND_BE;
|
|
case X86::JA: return X86::COND_A;
|
|
case X86::JAE: return X86::COND_AE;
|
|
case X86::JS: return X86::COND_S;
|
|
case X86::JNS: return X86::COND_NS;
|
|
case X86::JP: return X86::COND_P;
|
|
case X86::JNP: return X86::COND_NP;
|
|
case X86::JO: return X86::COND_O;
|
|
case X86::JNO: return X86::COND_NO;
|
|
}
|
|
}
|
|
|
|
unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
|
|
switch (CC) {
|
|
default: assert(0 && "Illegal condition code!");
|
|
case X86::COND_E: return X86::JE;
|
|
case X86::COND_NE: return X86::JNE;
|
|
case X86::COND_L: return X86::JL;
|
|
case X86::COND_LE: return X86::JLE;
|
|
case X86::COND_G: return X86::JG;
|
|
case X86::COND_GE: return X86::JGE;
|
|
case X86::COND_B: return X86::JB;
|
|
case X86::COND_BE: return X86::JBE;
|
|
case X86::COND_A: return X86::JA;
|
|
case X86::COND_AE: return X86::JAE;
|
|
case X86::COND_S: return X86::JS;
|
|
case X86::COND_NS: return X86::JNS;
|
|
case X86::COND_P: return X86::JP;
|
|
case X86::COND_NP: return X86::JNP;
|
|
case X86::COND_O: return X86::JO;
|
|
case X86::COND_NO: return X86::JNO;
|
|
}
|
|
}
|
|
|
|
/// GetOppositeBranchCondition - Return the inverse of the specified condition,
|
|
/// e.g. turning COND_E to COND_NE.
|
|
X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
|
|
switch (CC) {
|
|
default: assert(0 && "Illegal condition code!");
|
|
case X86::COND_E: return X86::COND_NE;
|
|
case X86::COND_NE: return X86::COND_E;
|
|
case X86::COND_L: return X86::COND_GE;
|
|
case X86::COND_LE: return X86::COND_G;
|
|
case X86::COND_G: return X86::COND_LE;
|
|
case X86::COND_GE: return X86::COND_L;
|
|
case X86::COND_B: return X86::COND_AE;
|
|
case X86::COND_BE: return X86::COND_A;
|
|
case X86::COND_A: return X86::COND_BE;
|
|
case X86::COND_AE: return X86::COND_B;
|
|
case X86::COND_S: return X86::COND_NS;
|
|
case X86::COND_NS: return X86::COND_S;
|
|
case X86::COND_P: return X86::COND_NP;
|
|
case X86::COND_NP: return X86::COND_P;
|
|
case X86::COND_O: return X86::COND_NO;
|
|
case X86::COND_NO: return X86::COND_O;
|
|
}
|
|
}
|
|
|
|
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
|
|
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
|
|
if (TID->Flags & M_TERMINATOR_FLAG) {
|
|
// Conditional branch is a special case.
|
|
if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
|
|
return true;
|
|
if ((TID->Flags & M_PREDICABLE) == 0)
|
|
return true;
|
|
return !isPredicated(MI);
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
|
|
static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
|
|
const X86InstrInfo &TII) {
|
|
if (MI->getOpcode() == X86::FP_REG_KILL)
|
|
return false;
|
|
return TII.isUnpredicatedTerminator(MI);
|
|
}
|
|
|
|
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
|
MachineBasicBlock *&TBB,
|
|
MachineBasicBlock *&FBB,
|
|
std::vector<MachineOperand> &Cond) const {
|
|
// If the block has no terminators, it just falls into the block after it.
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
|
|
return false;
|
|
|
|
// Get the last instruction in the block.
|
|
MachineInstr *LastInst = I;
|
|
|
|
// If there is only one terminator instruction, process it.
|
|
if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
|
|
if (!isBranch(LastInst->getOpcode()))
|
|
return true;
|
|
|
|
// If the block ends with a branch there are 3 possibilities:
|
|
// it's an unconditional, conditional, or indirect branch.
|
|
|
|
if (LastInst->getOpcode() == X86::JMP) {
|
|
TBB = LastInst->getOperand(0).getMachineBasicBlock();
|
|
return false;
|
|
}
|
|
X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
|
|
if (BranchCode == X86::COND_INVALID)
|
|
return true; // Can't handle indirect branch.
|
|
|
|
// Otherwise, block ends with fall-through condbranch.
|
|
TBB = LastInst->getOperand(0).getMachineBasicBlock();
|
|
Cond.push_back(MachineOperand::CreateImm(BranchCode));
|
|
return false;
|
|
}
|
|
|
|
// Get the instruction before it if it's a terminator.
|
|
MachineInstr *SecondLastInst = I;
|
|
|
|
// If there are three terminators, we don't know what sort of block this is.
|
|
if (SecondLastInst && I != MBB.begin() &&
|
|
isBrAnalysisUnpredicatedTerminator(--I, *this))
|
|
return true;
|
|
|
|
// If the block ends with X86::JMP and a conditional branch, handle it.
|
|
X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
|
|
if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
|
|
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
|
|
Cond.push_back(MachineOperand::CreateImm(BranchCode));
|
|
FBB = LastInst->getOperand(0).getMachineBasicBlock();
|
|
return false;
|
|
}
|
|
|
|
// If the block ends with two X86::JMPs, handle it. The second one is not
|
|
// executed, so remove it.
|
|
if (SecondLastInst->getOpcode() == X86::JMP &&
|
|
LastInst->getOpcode() == X86::JMP) {
|
|
TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
|
|
I = LastInst;
|
|
I->eraseFromParent();
|
|
return false;
|
|
}
|
|
|
|
// Otherwise, can't handle this.
|
|
return true;
|
|
}
|
|
|
|
unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
if (I == MBB.begin()) return 0;
|
|
--I;
|
|
if (I->getOpcode() != X86::JMP &&
|
|
GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
|
|
return 0;
|
|
|
|
// Remove the branch.
|
|
I->eraseFromParent();
|
|
|
|
I = MBB.end();
|
|
|
|
if (I == MBB.begin()) return 1;
|
|
--I;
|
|
if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
|
|
return 1;
|
|
|
|
// Remove the branch.
|
|
I->eraseFromParent();
|
|
return 2;
|
|
}
|
|
|
|
unsigned
|
|
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
const std::vector<MachineOperand> &Cond) const {
|
|
// Shouldn't be a fall through.
|
|
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
|
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
|
"X86 branch conditions have one component!");
|
|
|
|
if (FBB == 0) { // One way branch.
|
|
if (Cond.empty()) {
|
|
// Unconditional branch?
|
|
BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
|
|
} else {
|
|
// Conditional branch.
|
|
unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
|
|
BuildMI(&MBB, get(Opc)).addMBB(TBB);
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
// Two-way Conditional branch.
|
|
unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
|
|
BuildMI(&MBB, get(Opc)).addMBB(TBB);
|
|
BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
|
|
return 2;
|
|
}
|
|
|
|
bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
|
if (MBB.empty()) return false;
|
|
|
|
switch (MBB.back().getOpcode()) {
|
|
case X86::TCRETURNri:
|
|
case X86::TCRETURNdi:
|
|
case X86::RET: // Return.
|
|
case X86::RETI:
|
|
case X86::TAILJMPd:
|
|
case X86::TAILJMPr:
|
|
case X86::TAILJMPm:
|
|
case X86::JMP: // Uncond branch.
|
|
case X86::JMP32r: // Indirect branch.
|
|
case X86::JMP64r: // Indirect branch (64-bit).
|
|
case X86::JMP32m: // Indirect branch through mem.
|
|
case X86::JMP64m: // Indirect branch through mem (64-bit).
|
|
return true;
|
|
default: return false;
|
|
}
|
|
}
|
|
|
|
bool X86InstrInfo::
|
|
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
|
|
assert(Cond.size() == 1 && "Invalid X86 branch condition!");
|
|
Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
|
|
return false;
|
|
}
|
|
|
|
const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
|
|
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
|
|
if (Subtarget->is64Bit())
|
|
return &X86::GR64RegClass;
|
|
else
|
|
return &X86::GR32RegClass;
|
|
}
|