mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 22:29:56 +00:00
36b7beb429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
191 lines
4.6 KiB
LLVM
191 lines
4.6 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; Test sitofp
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define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
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entry:
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; ARM: sitofp_single_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.s32 s0, s0
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; THUMB: sitofp_single_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.s32 s0, s0
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%b.addr = alloca float, align 4
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%conv = sitofp i32 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
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entry:
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; ARM: sitofp_single_i16
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; ARM: sxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.s32 s0, s0
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; THUMB: sitofp_single_i16
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; THUMB: sxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.s32 s0, s0
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%b.addr = alloca float, align 4
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%conv = sitofp i16 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i8(i8 %a) nounwind ssp {
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entry:
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; ARM: sitofp_single_i8
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; ARM: sxtb r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.s32 s0, s0
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; THUMB: sitofp_single_i8
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; THUMB: sxtb r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.s32 s0, s0
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%b.addr = alloca float, align 4
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%conv = sitofp i8 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ARM: sitofp_double_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.s32 d16, s0
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; THUMB: sitofp_double_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.s32 d16, s0
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%b.addr = alloca double, align 8
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%conv = sitofp i32 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
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entry:
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; ARM: sitofp_double_i16
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; ARM: sxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.s32 d16, s0
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; THUMB: sitofp_double_i16
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; THUMB: sxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.s32 d16, s0
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%b.addr = alloca double, align 8
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%conv = sitofp i16 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
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entry:
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; ARM: sitofp_double_i8
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; ARM: sxtb r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.s32 d16, s0
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; THUMB: sitofp_double_i8
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; THUMB: sxtb r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.s32 d16, s0
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%b.addr = alloca double, align 8
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%conv = sitofp i8 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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; Test uitofp
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define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
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entry:
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; ARM: uitofp_single_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.u32 s0, s0
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; THUMB: uitofp_single_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.u32 s0, s0
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%b.addr = alloca float, align 4
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%conv = uitofp i32 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
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entry:
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; ARM: uitofp_single_i16
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; ARM: uxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.u32 s0, s0
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; THUMB: uitofp_single_i16
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; THUMB: uxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.u32 s0, s0
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%b.addr = alloca float, align 4
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%conv = uitofp i16 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i8(i8 %a) nounwind ssp {
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entry:
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; ARM: uitofp_single_i8
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; ARM: uxtb r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.u32 s0, s0
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; THUMB: uitofp_single_i8
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; THUMB: uxtb r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.u32 s0, s0
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%b.addr = alloca float, align 4
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%conv = uitofp i8 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ARM: uitofp_double_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.u32 d16, s0
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; THUMB: uitofp_double_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.u32 d16, s0
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%b.addr = alloca double, align 8
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%conv = uitofp i32 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
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entry:
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; ARM: uitofp_double_i16
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; ARM: uxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.u32 d16, s0
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; THUMB: uitofp_double_i16
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; THUMB: uxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.u32 d16, s0
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%b.addr = alloca double, align 8
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%conv = uitofp i16 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
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entry:
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; ARM: uitofp_double_i8
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; ARM: uxtb r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.u32 d16, s0
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; THUMB: uitofp_double_i8
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; THUMB: uxtb r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.u32 d16, s0
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%b.addr = alloca double, align 8
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%conv = uitofp i8 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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