llvm-6502/test/CodeGen/ARM/fpconsts.ll
Andrew Trick c8bfd1d78f Convert -enable-sched-cycles and -enable-sched-hazard to -disable
flags. They are still not enable in this revision.

Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.

Generalized unit tests to work with sched-cycles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21 05:51:33 +00:00

34 lines
743 B
LLVM

; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s
define float @t1(float %x) nounwind readnone optsize {
entry:
; CHECK: t1:
; CHECK: vmov.f32 s{{.*}}, #4.000000e+00
%0 = fadd float %x, 4.000000e+00
ret float %0
}
define double @t2(double %x) nounwind readnone optsize {
entry:
; CHECK: t2:
; CHECK: vmov.f64 d{{.*}}, #3.000000e+00
%0 = fadd double %x, 3.000000e+00
ret double %0
}
define double @t3(double %x) nounwind readnone optsize {
entry:
; CHECK: t3:
; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01
%0 = fmul double %x, -1.300000e+01
ret double %0
}
define float @t4(float %x) nounwind readnone optsize {
entry:
; CHECK: t4:
; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01
%0 = fmul float %x, -2.400000e+01
ret float %0
}