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ec716cecda
isel is actually a cracked instruction on the P7/P8, and must start a dispatch group. The scheduling model should reflect this so that we don't bunch too many of them together when possible. Thanks to Bill Schmidt and Pat Haugen for helping to sort this out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227758 91177308-0d34-0410-b5e6-96231b3b80d8
402 lines
23 KiB
TableGen
402 lines
23 KiB
TableGen
//===-- PPCScheduleP8.td - PPC P8 Scheduling Definitions ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the POWER8 processor.
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//
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//===----------------------------------------------------------------------===//
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// Scheduling for the P8 involves tracking two types of resources:
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// 1. The dispatch bundle slots
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// 2. The functional unit resources
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// Dispatch units:
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def P8_DU1 : FuncUnit;
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def P8_DU2 : FuncUnit;
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def P8_DU3 : FuncUnit;
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def P8_DU4 : FuncUnit;
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def P8_DU5 : FuncUnit;
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def P8_DU6 : FuncUnit;
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def P8_DU7 : FuncUnit; // Only branch instructions will use DU7,DU8
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def P8_DU8 : FuncUnit;
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// 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
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def P8_LU1 : FuncUnit; // Loads or fixed-point operations 1
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def P8_LU2 : FuncUnit; // Loads or fixed-point operations 2
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// Load/Store pipelines can handle Stores, fixed-point loads, and simple
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// fixed-point operations.
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def P8_LSU1 : FuncUnit; // Load/Store pipeline 1
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def P8_LSU2 : FuncUnit; // Load/Store pipeline 2
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// Fixed Point unit
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def P8_FXU1 : FuncUnit; // FX pipeline 1
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def P8_FXU2 : FuncUnit; // FX pipeline 2
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// The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
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// are combined on P7 and newer into a Vector Scalar Unit (VSU).
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// The P8 Instruction latency documents still refers to the unit as the
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// FPU, so keep in mind that FPU==VSU.
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// In contrast to the P7, the VMX units on P8 are symmetric, so no need to
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// split vector integer ops or 128-bit load/store/perms to the specific units.
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def P8_FPU1 : FuncUnit; // VS pipeline 1
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def P8_FPU2 : FuncUnit; // VS pipeline 2
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def P8_CRU : FuncUnit; // CR unit (CR logicals and move-from-SPRs)
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def P8_BRU : FuncUnit; // BR unit
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def P8Itineraries : ProcessorItineraries<
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[P8_DU1, P8_DU2, P8_DU3, P8_DU4, P8_DU5, P8_DU6, P8_DU7, P8_DU8,
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P8_LU1, P8_LU2, P8_LSU1, P8_LSU2, P8_FXU1, P8_FXU2,
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P8_FPU1, P8_FPU2, P8_CRU, P8_BRU], [], [
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InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2,
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P8_LU1, P8_LU2,
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P8_LSU1, P8_LSU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1,
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P8_LU2, P8_LSU1, P8_LSU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
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InstrStage<1, [P8_BRU]>],
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[1, 1, 1, 1]>,
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InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<15, [P8_FXU1, P8_FXU2]>],
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[15, 1, 1]>,
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InstrItinData<IIC_IntDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<23, [P8_FXU1, P8_FXU2]>],
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[23, 1, 1]>,
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InstrItinData<IIC_IntMulHW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[4, 1, 1]>,
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InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[4, 1, 1]>,
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InstrItinData<IIC_IntMulLI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[4, 1, 1]>,
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InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntRotateD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntShift , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntTrapW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[1, 1]>,
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InstrItinData<IIC_IntTrapD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[1, 1]>,
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InstrItinData<IIC_BrB , [InstrStage<1, [P8_DU7, P8_DU8], 0>,
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InstrStage<1, [P8_BRU]>],
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[3, 1, 1]>,
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// FIXME - the Br* groups below are not branch related, so should probably
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// be renamed.
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// IIC_BrCR consists of the cr* instructions. (crand,crnor,creqv, etc).
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// and should be 'First' in dispatch.
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InstrItinData<IIC_BrCR , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_CRU]>],
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[3, 1, 1]>,
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// IIC_BrMCR consists of the mcrf instruction.
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InstrItinData<IIC_BrMCR , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_CRU]>],
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[3, 1, 1]>,
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// IIC_BrMCRX consists of mcrxr (obsolete instruction) and mtcrf, which
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// should be first in the dispatch group.
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InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[3, 1]>,
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InstrItinData<IIC_LdStLoad , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2]>],
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[2, 1, 1]>,
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InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2 ], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[2, 2, 1, 1]>,
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// Update-Indexed form loads/stores are no longer first and last in the
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// dispatch group. They are simply cracked, so require DU1,DU2.
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InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[3, 3, 1, 1]>,
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InstrItinData<IIC_LdStLD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2]>],
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[2, 1, 1]>,
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InstrItinData<IIC_LdStLDU , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[2, 2, 1, 1]>,
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InstrItinData<IIC_LdStLDUX , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[3, 3, 1, 1]>,
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InstrItinData<IIC_LdStLFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_LU1, P8_LU2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLVecX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_LU1, P8_LU2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLFDU , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LU1, P8_LU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[3, 3, 1, 1]>,
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InstrItinData<IIC_LdStLFDUX , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LU1, P8_LU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[3, 3, 1, 1]>,
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InstrItinData<IIC_LdStLHA , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2,
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P8_LU1, P8_LU2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLHAU , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[4, 4, 1, 1]>,
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// first+last in dispatch group.
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InstrItinData<IIC_LdStLHAUX , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_DU3], 0>,
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InstrStage<1, [P8_DU4], 0>,
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InstrStage<1, [P8_DU5], 0>,
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InstrStage<1, [P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[4, 4, 1, 1]>,
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InstrItinData<IIC_LdStLWA , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2]>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_DU3], 0>,
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InstrStage<1, [P8_DU4], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2]>],
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[3, 1, 1]>,
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// first+last
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InstrItinData<IIC_LdStLDARX, [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_DU3], 0>,
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InstrStage<1, [P8_DU4], 0>,
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InstrStage<1, [P8_DU5], 0>,
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InstrStage<1, [P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2]>],
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[3, 1, 1]>,
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InstrItinData<IIC_LdStLMW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2,
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P8_LU1, P8_LU2]>],
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[2, 1, 1]>,
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// Stores are dual-issued from the issue queue, so may only take up one
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// dispatch slot. The instruction will be broken into two IOPS. The agen
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// op is issued to the LSU, and the data op (register fetch) is issued
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// to either the LU (GPR store) or the VSU (FPR store).
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InstrItinData<IIC_LdStStore , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2]>,
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InstrStage<1, [P8_LU1, P8_LU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_LU1, P8_LU2,
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P8_LSU1, P8_LSU2]>]
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTDU , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LU1, P8_LU2,
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P8_LSU1, P8_LSU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[2, 1, 1, 1]>,
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// First+last
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InstrItinData<IIC_LdStSTDUX , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_DU3], 0>,
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InstrStage<1, [P8_DU4], 0>,
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InstrStage<1, [P8_DU5], 0>,
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InstrStage<1, [P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[2, 1, 1, 1]>,
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InstrItinData<IIC_LdStSTFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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InstrStage<1, [P8_FPU1, P8_FPU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTFDU , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
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InstrStage<1, [P8_FPU1, P8_FPU2]>],
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[2, 1, 1, 1]>,
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InstrItinData<IIC_LdStSTVEBX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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InstrStage<1, [P8_FPU1, P8_FPU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTDCX , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_DU3], 0>,
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InstrStage<1, [P8_DU4], 0>,
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InstrStage<1, [P8_DU5], 0>,
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InstrStage<1, [P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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InstrStage<1, [P8_LU1, P8_LU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_LdStSTWCX , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_DU2], 0>,
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InstrStage<1, [P8_DU3], 0>,
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InstrStage<1, [P8_DU4], 0>,
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InstrStage<1, [P8_DU5], 0>,
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InstrStage<1, [P8_DU6], 0>,
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InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
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InstrStage<1, [P8_LU1, P8_LU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_SprMFCR , [InstrStage<1, [P8_DU1], 0>,
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InstrStage<1, [P8_CRU]>],
|
|
[6, 1]>,
|
|
InstrItinData<IIC_SprMFCRF , [InstrStage<1, [P8_DU1], 0>,
|
|
InstrStage<1, [P8_CRU]>],
|
|
[3, 1]>,
|
|
InstrItinData<IIC_SprMTSPR , [InstrStage<1, [P8_DU1], 0>,
|
|
InstrStage<1, [P8_FXU1, P8_FXU2]>],
|
|
[4, 1]>, // mtctr
|
|
InstrItinData<IIC_FPGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
|
|
P8_DU4, P8_DU5, P8_DU6], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[5, 1, 1]>,
|
|
InstrItinData<IIC_FPCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
|
|
P8_DU4, P8_DU5, P8_DU6], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[8, 1, 1]>,
|
|
InstrItinData<IIC_FPDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
|
|
P8_DU4, P8_DU5, P8_DU6], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[33, 1, 1]>,
|
|
InstrItinData<IIC_FPDivS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
|
|
P8_DU4, P8_DU5, P8_DU6], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[27, 1, 1]>,
|
|
InstrItinData<IIC_FPSqrtD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
|
|
P8_DU4, P8_DU5, P8_DU6], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[44, 1, 1]>,
|
|
InstrItinData<IIC_FPSqrtS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
|
|
P8_DU4, P8_DU5, P8_DU6], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[32, 1, 1]>,
|
|
InstrItinData<IIC_FPFused , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
|
|
P8_DU4, P8_DU5, P8_DU6], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[5, 1, 1, 1]>,
|
|
InstrItinData<IIC_FPRes , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
|
|
P8_DU4, P8_DU5, P8_DU6], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[5, 1, 1]>,
|
|
InstrItinData<IIC_VecGeneral , [InstrStage<1, [P8_DU1], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[2, 1, 1]>,
|
|
InstrItinData<IIC_VecVSL , [InstrStage<1, [P8_DU1], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[2, 1, 1]>,
|
|
InstrItinData<IIC_VecVSR , [InstrStage<1, [P8_DU1], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[2, 1, 1]>,
|
|
InstrItinData<IIC_VecFP , [InstrStage<1, [P8_DU1], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[6, 1, 1]>,
|
|
InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P8_DU1], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[6, 1, 1]>,
|
|
InstrItinData<IIC_VecFPRound , [InstrStage<1, [P8_DU1], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[6, 1, 1]>,
|
|
InstrItinData<IIC_VecComplex , [InstrStage<1, [P8_DU1], 0>,
|
|
InstrStage<1, [P8_FPU1, P8_FPU2]>],
|
|
[7, 1, 1]>,
|
|
InstrItinData<IIC_VecPerm , [InstrStage<1, [P8_DU1, P8_DU2], 0>,
|
|
InstrStage<1, [P8_FPU2, P8_FPU2]>],
|
|
[3, 1, 1]>
|
|
]>;
|
|
|
|
// ===---------------------------------------------------------------------===//
|
|
// P8 machine model for scheduling and other instruction cost heuristics.
|
|
// P8 has an 8 insn dispatch group (6 non-branch, 2 branch) and can issue up
|
|
// to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
|
|
|
|
def P8Model : SchedMachineModel {
|
|
let IssueWidth = 8; // up to 8 instructions dispatched per cycle.
|
|
// up to six non-branch instructions.
|
|
// up to two branches in a dispatch group.
|
|
|
|
let MinLatency = 0; // Out-of-order dispatch.
|
|
let LoadLatency = 3; // Optimistic load latency assuming bypass.
|
|
// This is overriden by OperandCycles if the
|
|
// Itineraries are queried instead.
|
|
let MispredictPenalty = 16;
|
|
|
|
// Try to make sure we have at least 10 dispatch groups in a loop.
|
|
let LoopMicroOpBufferSize = 60;
|
|
|
|
let Itineraries = P8Itineraries;
|
|
}
|
|
|