Evan Cheng f229a5d4be Bottom up register-pressure reduction scheduler now pushes store operations ... up the schedule. This helps code that looks like this: loads ... computations (first set) ... stores (first set) ... loads computations (seccond set) ... stores (seccond set) ... Without this change, the stores and computations are more likely to interleave: loads ... loads ... computations (first set) ... computations (second set) ... computations (first set) ... stores (first set) ... computations (second set) ... stores (stores set) ... This can increase the number of spills if we are unlucky. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28033 91177308-0d34-0410-b5e6-96231b3b80d8		2006-05-01 09:14:40 +00:00
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Analysis	Implement Transforms/IndVarsSimplify/complex-scev.ll, a case where we didn't	2006-04-26 18:34:07 +00:00
Archive	more C++ daintiness	2005-12-26 14:31:26 +00:00
AsmParser	Make sure CVS versions of yacc and lex files get distributed.	2006-04-12 20:57:05 +00:00
Bytecode	use isValidOperands instead of duplicating checks	2006-04-08 04:09:19 +00:00
CodeGen	Bottom up register-pressure reduction scheduler now pushes store operations	2006-05-01 09:14:40 +00:00
Debugger	Add the README files to the distribution.	2006-04-13 06:39:24 +00:00
ExecutionEngine	Fix a warning	2006-04-25 17:46:32 +00:00
Linker	Add shufflevector support	2006-04-08 01:19:47 +00:00
Support	Fix PR743: emit -help output of a tool to cout, not cerr.	2006-04-28 05:36:25 +00:00
System	Mingw32 patches supplied by Anton Korobeynikov.	2006-04-29 18:41:44 +00:00
Target	Remove %'s from register names when in intel mode.	2006-05-01 05:53:50 +00:00
Transforms	Fix InstCombine/2006-04-28-ShiftShiftLongLong.ll	2006-04-28 22:21:41 +00:00
VMCore	Remove a hack required by V9.	2006-04-21 15:33:35 +00:00
Makefile