mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2cda6e8ca6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211376 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
3.0 KiB
LLVM
80 lines
3.0 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK --check-prefix=FUNC
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;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK --check-prefix=FUNC
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;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC
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;FUNC-LABEL: @test
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;EG-CHECK: LOG_IEEE
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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;SI-CHECK: V_LOG_F32
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define void @test(float addrspace(1)* %out, float %in) {
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entry:
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%0 = call float @llvm.log2.f32(float %in)
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store float %0, float addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: @testv2
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;EG-CHECK: LOG_IEEE
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;EG-CHECK: LOG_IEEE
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; FIXME: We should be able to merge these packets together on Cayman so we
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; have a maximum of 4 instructions.
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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;SI-CHECK: V_LOG_F32
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;SI-CHECK: V_LOG_F32
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define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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entry:
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%0 = call <2 x float> @llvm.log2.v2f32(<2 x float> %in)
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: @testv4
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;EG-CHECK: LOG_IEEE
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;EG-CHECK: LOG_IEEE
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;EG-CHECK: LOG_IEEE
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;EG-CHECK: LOG_IEEE
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; FIXME: We should be able to merge these packets together on Cayman so we
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; have a maximum of 4 instructions.
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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;CM-CHECK-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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;SI-CHECK: V_LOG_F32
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;SI-CHECK: V_LOG_F32
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;SI-CHECK: V_LOG_F32
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;SI-CHECK: V_LOG_F32
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define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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entry:
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%0 = call <4 x float> @llvm.log2.v4f32(<4 x float> %in)
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store <4 x float> %0, <4 x float> addrspace(1)* %out
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ret void
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}
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declare float @llvm.log2.f32(float) readnone
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declare <2 x float> @llvm.log2.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.log2.v4f32(<4 x float>) readnone
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