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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
6824f127f9
System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8
174 lines
4.6 KiB
LLVM
174 lines
4.6 KiB
LLVM
; Test 32-bit atomic minimum and maximum.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check signed minium.
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define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: crjle %r2, %r4, [[KEEP:\..*]]
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; CHECK: lr [[NEW]], %r4
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jl [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw min i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check signed maximum.
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define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f2:
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: crjhe %r2, %r4, [[KEEP:\..*]]
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; CHECK: lr [[NEW]], %r4
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jl [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw max i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check unsigned minimum.
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define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: clr %r2, %r4
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: jle [[KEEP:\..*]]
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; CHECK: lr [[NEW]], %r4
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jl [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw umin i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check unsigned maximum.
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define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f4:
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: clr %r2, %r4
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: jhe [[KEEP:\..*]]
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; CHECK: lr [[NEW]], %r4
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jl [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw umax i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check the high end of the aligned CS range.
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define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f5:
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; CHECK: l %r2, 4092(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1023
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word up, which requires CSY.
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define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: ly %r2, 4096(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1024
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the high end of the aligned CSY range.
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define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f7:
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; CHECK: ly %r2, 524284(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131071
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word up, which needs separate address logic.
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define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r3, 524288
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; CHECK: l %r2, 0(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131072
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the high end of the negative aligned CSY range.
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define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f9:
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; CHECK: ly %r2, -4(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -1
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the low end of the CSY range.
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define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: ly %r2, -524288(%r3)
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; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131072
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word down, which needs separate address logic.
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define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f11:
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; CHECK: agfi %r3, -524292
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; CHECK: l %r2, 0(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131073
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check that indexed addresses are not allowed.
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define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
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; CHECK-LABEL: f12:
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; CHECK: agr %r3, %r4
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; CHECK: l %r2, 0(%r3)
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; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
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; CHECK: br %r14
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%add = add i64 %base, %index
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%ptr = inttoptr i64 %add to i32 *
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%res = atomicrmw min i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check that constants are handled.
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define i32 @f13(i32 %dummy, i32 *%ptr) {
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; CHECK-LABEL: f13:
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; CHECK: lhi [[LIMIT:%r[0-9]+]], 42
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; CHECK: l %r2, 0(%r3)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: lr [[NEW:%r[0-9]+]], %r2
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; CHECK: crjle %r2, [[LIMIT]], [[KEEP:\..*]]
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; CHECK: lhi [[NEW]], 42
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; CHECK: cs %r2, [[NEW]], 0(%r3)
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; CHECK: jl [[LOOP]]
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; CHECK: br %r14
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%res = atomicrmw min i32 *%ptr, i32 42 seq_cst
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ret i32 %res
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}
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