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https://github.com/c64scene-ar/llvm-6502.git
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8950dd127a
The assembler currently strictly verifies that immediates for s16imm operands are in range (-32768 ... 32767). This matches the behaviour of the GNU assembler, with one exception: gas allows, as a special case, operands in an extended range (-65536 .. 65535) for the addis instruction only (and its extended mnemonic lis). The main reason for this seems to be to allow using unsigned 16-bit operands for lis, e.g. like lis %r1, 0xfedc. Since this has been supported by gas for a long time, and assembler source code seen "in the wild" actually exploits this feature, this patch adds equivalent support to LLVM for compatibility reasons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184946 91177308-0d34-0410-b5e6-96231b3b80d8
111 lines
3.3 KiB
ArmAsm
111 lines
3.3 KiB
ArmAsm
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# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
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# Register operands
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# CHECK: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14]
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add 1, 2, 3
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# CHECK: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14]
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add %r1, %r2, %r3
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# CHECK: add 0, 0, 0 # encoding: [0x7c,0x00,0x02,0x14]
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add 0, 0, 0
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# CHECK: add 31, 31, 31 # encoding: [0x7f,0xff,0xfa,0x14]
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add 31, 31, 31
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# CHECK: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00]
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addi 1, 0, 0
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# CHECK: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00]
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addi 1, %r0, 0
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# Signed 16-bit immediate operands
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# CHECK: addi 1, 2, 0 # encoding: [0x38,0x22,0x00,0x00]
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addi 1, 2, 0
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# CHECK: addi 1, 0, -32768 # encoding: [0x38,0x20,0x80,0x00]
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addi 1, 0, -32768
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# CHECK: addi 1, 0, 32767 # encoding: [0x38,0x20,0x7f,0xff]
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addi 1, 0, 32767
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# Unsigned 16-bit immediate operands
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# CHECK: ori 1, 2, 0 # encoding: [0x60,0x41,0x00,0x00]
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ori 1, 2, 0
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# CHECK: ori 1, 2, 65535 # encoding: [0x60,0x41,0xff,0xff]
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ori 1, 2, 65535
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# Signed 16-bit immediate operands (extended range for addis)
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# CHECK: addis 1, 0, 0 # encoding: [0x3c,0x20,0x00,0x00]
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addis 1, 0, -65536
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# CHECK: addis 1, 0, -1 # encoding: [0x3c,0x20,0xff,0xff]
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addis 1, 0, 65535
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# D-Form memory operands
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# CHECK: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00]
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lwz 1, 0(0)
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# CHECK: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00]
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lwz 1, 0(%r0)
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# CHECK: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00]
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lwz 1, 0(31)
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# CHECK: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00]
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lwz 1, 0(%r31)
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# CHECK: lwz 1, -32768(2) # encoding: [0x80,0x22,0x80,0x00]
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lwz 1, -32768(2)
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# CHECK: lwz 1, 32767(2) # encoding: [0x80,0x22,0x7f,0xff]
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lwz 1, 32767(2)
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# CHECK: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00]
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ld 1, 0(0)
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# CHECK: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00]
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ld 1, 0(%r0)
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# CHECK: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00]
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ld 1, 0(31)
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# CHECK: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00]
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ld 1, 0(%r31)
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# CHECK: ld 1, -32768(2) # encoding: [0xe8,0x22,0x80,0x00]
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ld 1, -32768(2)
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# CHECK: ld 1, 32764(2) # encoding: [0xe8,0x22,0x7f,0xfc]
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ld 1, 32764(2)
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# CHECK: ld 1, 4(2) # encoding: [0xe8,0x22,0x00,0x04]
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ld 1, 4(2)
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# CHECK: ld 1, -4(2) # encoding: [0xe8,0x22,0xff,0xfc]
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ld 1, -4(2)
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# Immediate branch operands
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# CHECK: b .+1024 # encoding: [0x48,0x00,0x04,0x00]
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b 1024
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# CHECK: ba 1024 # encoding: [0x48,0x00,0x04,0x02]
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ba 1024
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# CHECK: beq 0, .+1024 # encoding: [0x41,0x82,0x04,0x00]
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beq 1024
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# CHECK: beqa 0, 1024 # encoding: [0x41,0x82,0x04,0x02]
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beqa 1024
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