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https://github.com/c64scene-ar/llvm-6502.git
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6cadd406cc
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203281 91177308-0d34-0410-b5e6-96231b3b80d8
143 lines
4.3 KiB
LLVM
143 lines
4.3 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s
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;FUNC-LABEL: @test1:
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}}
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;SI-CHECK-NOT: [[REG]]
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;SI-CHECK: BUFFER_STORE_DWORD [[REG]],
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define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%a = load i32 addrspace(1)* %in
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%b = load i32 addrspace(1)* %b_ptr
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%result = add i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: @test2:
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32> addrspace(1)* %in
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%b = load <2 x i32> addrspace(1)* %b_ptr
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%result = add <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: @test4:
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32> addrspace(1)* %in
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%b = load <4 x i32> addrspace(1)* %b_ptr
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%result = add <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @test8
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
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entry:
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%0 = add <8 x i32> %a, %b
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store <8 x i32> %0, <8 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @test16
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADD_I32
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define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) {
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entry:
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%0 = add <16 x i32> %a, %b
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store <16 x i32> %0, <16 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @add64
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; SI-CHECK: S_ADD_I32
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; SI-CHECK: S_ADDC_U32
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define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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entry:
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%0 = add i64 %a, %b
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store i64 %0, i64 addrspace(1)* %out
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ret void
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}
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; The V_ADDC_U32 and V_ADD_I32 instruction can't read SGPRs, because they
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; use VCC. The test is designed so that %a will be stored in an SGPR and
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; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
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; to a VGPR before doing the add.
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; FUNC-LABEL: @add64_sgpr_vgpr
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; SI-CHECK-NOT: V_ADDC_U32_e32 s
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define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
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entry:
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%0 = load i64 addrspace(1)* %in
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%1 = add i64 %a, %0
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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