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f3157be108
and update initialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215280 91177308-0d34-0410-b5e6-96231b3b80d8
294 lines
9.3 KiB
C++
294 lines
9.3 KiB
C++
//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PPC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCSubtarget.h"
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#include "PPC.h"
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#include "PPCRegisterInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cstdlib>
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using namespace llvm;
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#define DEBUG_TYPE "ppc-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "PPCGenSubtargetInfo.inc"
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/// Return the datalayout string of a subtarget.
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static std::string getDataLayoutString(const PPCSubtarget &ST) {
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const Triple &T = ST.getTargetTriple();
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std::string Ret;
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// Most PPC* platforms are big endian, PPC64LE is little endian.
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if (ST.isLittleEndian())
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Ret = "e";
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else
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Ret = "E";
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Ret += DataLayout::getManglingComponent(T);
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// PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
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// pointers.
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if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
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Ret += "-p:32:32";
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// Note, the alignment values for f64 and i64 on ppc64 in Darwin
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// documentation are wrong; these are correct (i.e. "what gcc does").
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if (ST.isPPC64() || ST.isSVR4ABI())
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Ret += "-i64:64";
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else
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Ret += "-f64:32:64";
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// PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
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if (ST.isPPC64())
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Ret += "-n32:64";
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else
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Ret += "-n32";
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return Ret;
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}
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PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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return *this;
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}
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PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, PPCTargetMachine &TM,
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CodeGenOpt::Level OptLevel)
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: PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
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IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
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TargetTriple.getArch() == Triple::ppc64le),
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OptLevel(OptLevel), TargetABI(PPC_ABI_UNKNOWN),
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FrameLowering(initializeSubtargetDependencies(CPU, FS)),
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DL(getDataLayoutString(*this)), InstrInfo(*this), JITInfo(*this),
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TLInfo(TM), TSInfo(&DL) {}
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/// SetJITMode - This is called to inform the subtarget info that we are
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/// producing code for the JIT.
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void PPCSubtarget::SetJITMode() {
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// JIT mode doesn't want lazy resolver stubs, it knows exactly where
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// everything is. This matters for PPC64, which codegens in PIC mode without
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// stubs.
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HasLazyResolverStubs = false;
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// Calls to external functions need to use indirect calls
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IsJITCodeModel = true;
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}
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void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
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AttributeSet FnAttrs = MF->getFunction()->getAttributes();
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Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-cpu");
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Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-features");
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std::string CPU =
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!CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
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std::string FS =
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!FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
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if (!FS.empty()) {
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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}
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}
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void PPCSubtarget::initializeEnvironment() {
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StackAlignment = 16;
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DarwinDirective = PPC::DIR_NONE;
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HasMFOCRF = false;
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Has64BitSupport = false;
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Use64BitRegs = false;
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UseCRBits = false;
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HasAltivec = false;
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HasSPE = false;
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HasQPX = false;
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HasVSX = false;
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HasFCPSGN = false;
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HasFSQRT = false;
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HasFRE = false;
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HasFRES = false;
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HasFRSQRTE = false;
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HasFRSQRTES = false;
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HasRecipPrec = false;
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HasSTFIWX = false;
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HasLFIWAX = false;
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HasFPRND = false;
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HasFPCVT = false;
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HasISEL = false;
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HasPOPCNTD = false;
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HasLDBRX = false;
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IsBookE = false;
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IsPPC4xx = false;
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IsPPC6xx = false;
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IsE500 = false;
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DeprecatedMFTB = false;
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DeprecatedDST = false;
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HasLazyResolverStubs = false;
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IsJITCodeModel = false;
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}
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void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
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// Determine default and user specified characteristics
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "generic";
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#if (defined(__APPLE__) || defined(__linux__)) && \
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(defined(__ppc__) || defined(__powerpc__))
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if (CPUName == "generic")
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CPUName = sys::getHostCPUName();
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#endif
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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// Make sure 64-bit features are available when CPUname is generic
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std::string FullFS = FS;
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// If we are generating code for ppc64, verify that options make sense.
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if (IsPPC64) {
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Has64BitSupport = true;
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// Silently force 64-bit register use on ppc64.
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Use64BitRegs = true;
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if (!FullFS.empty())
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FullFS = "+64bit," + FullFS;
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else
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FullFS = "+64bit";
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}
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// At -O2 and above, track CR bits as individual registers.
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if (OptLevel >= CodeGenOpt::Default) {
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if (!FullFS.empty())
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FullFS = "+crbits," + FullFS;
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else
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FullFS = "+crbits";
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}
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FullFS);
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// If the user requested use of 64-bit regs, but the cpu selected doesn't
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// support it, ignore.
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if (use64BitRegs() && !has64BitSupport())
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Use64BitRegs = false;
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// Set up darwin-specific properties.
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if (isDarwin())
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HasLazyResolverStubs = true;
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// QPX requires a 32-byte aligned stack. Note that we need to do this if
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// we're compiling for a BG/Q system regardless of whether or not QPX
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// is enabled because external functions will assume this alignment.
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if (hasQPX() || isBGQ())
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StackAlignment = 32;
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// Determine endianness.
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IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
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// FIXME: For now, we disable VSX in little-endian mode until endian
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// issues in those instructions can be addressed.
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if (IsLittleEndian)
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HasVSX = false;
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// Determine default ABI.
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if (TargetABI == PPC_ABI_UNKNOWN) {
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if (!isDarwin() && IsPPC64) {
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if (IsLittleEndian)
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TargetABI = PPC_ABI_ELFv2;
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else
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TargetABI = PPC_ABI_ELFv1;
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}
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}
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}
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/// hasLazyResolverStub - Return true if accesses to the specified global have
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/// to go through a dyld lazy resolution stub. This means that an extra load
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/// is required to get the address of the global.
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bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
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const TargetMachine &TM) const {
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// We never have stubs if HasLazyResolverStubs=false or if in static mode.
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if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
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return false;
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// If symbol visibility is hidden, the extra load is not needed if
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// the symbol is definitely defined in the current translation unit.
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bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
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if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
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return false;
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return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
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GV->hasCommonLinkage() || isDecl;
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}
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// Embedded cores need aggressive scheduling (and some others also benefit).
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static bool needsAggressiveScheduling(unsigned Directive) {
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switch (Directive) {
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default: return false;
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case PPC::DIR_440:
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case PPC::DIR_A2:
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case PPC::DIR_E500mc:
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case PPC::DIR_E5500:
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case PPC::DIR_PWR7:
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case PPC::DIR_PWR8:
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return true;
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}
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}
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bool PPCSubtarget::enableMachineScheduler() const {
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// Enable MI scheduling for the embedded cores.
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// FIXME: Enable this for all cores (some additional modeling
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// may be necessary).
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return needsAggressiveScheduling(DarwinDirective);
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}
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// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
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bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
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PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
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return TargetSubtargetInfo::ANTIDEP_ALL;
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}
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void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(isPPC64() ?
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&PPC::G8RCRegClass : &PPC::GPRCRegClass);
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}
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void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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MachineInstr *begin,
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MachineInstr *end,
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unsigned NumRegionInstrs) const {
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if (needsAggressiveScheduling(DarwinDirective)) {
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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}
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// Spilling is generally expensive on all PPC cores, so always enable
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// register-pressure tracking.
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Policy.ShouldTrackPressure = true;
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}
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bool PPCSubtarget::useAA() const {
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// Use AA during code generation for the embedded cores.
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return needsAggressiveScheduling(DarwinDirective);
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}
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