llvm-6502/utils
Petr Pavlu d2e1e42c1a [TableGen] Improve decoding options for non-orthogonal instructions
When FixedLenDecoder matches an input bitpattern of form [01]+ with an
instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are
mixed/variable bits) it passes the input bitpattern to a specific instruction
decoder method which then makes a final decision whether the bitpattern is a
valid instruction or not. This means the decoder must handle all possible
values of the variable bits which sometimes leads to opcode rewrites in the
decoder method when the instructions are not fully orthogonal.

The patch provides a way for the decoder method to say that when it returns
Fail it does not necessarily mean the bitpattern is invalid, but rather that
the bitpattern is definitely not an instruction that is recognized by the
decoder method. The decoder can then try to match the input bitpattern with
other possible instruction bitpatterns.

For example, this allows to solve a situation on AArch64 where the `MSR
(immediate)` instruction has form:
1101 0101 0000 0??? 0100 ???? ???1 1111
but not all values of the ? bits are allowed. The rejected values should be
handled by the `extended MSR (register)` instruction:
1101 0101 000? ???? ???? ???? ???? ????

The decoder will first try to decode an input bitpattern that matches both
bitpatterns as `MSR (immediate)` but currently this puts the decoder method of
`MSR (immediate)` into a situation when it must be able to decode all possible
values of the ? bits, i.e. it would need to rewrite the instruction to `MSR
(register)` when it is not `MSR (immediate)`.

The patch allows to specify that the decoder method cannot determine if the
instruction is valid for all variable values. The decoder method can simply
return Fail when it knows it is definitely not `MSR (immediate)`. The decoder
will then backtrack the decoding and find that it can match the input
bitpattern with the more generic `MSR (register)` bitpattern too.

Differential Revision: http://reviews.llvm.org/D7174


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242274 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-15 08:04:27 +00:00
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bugpoint
buildit
count
crosstool
emacs
FileCheck Replace push_back(Constructor(foo)) with emplace_back(foo) for non-trivial types 2015-05-29 19:43:39 +00:00
fpcmp
git
git-svn Improve check on git-svnrevert, better error message 2015-05-16 10:23:48 +00:00
jedit
kate
KillTheDoctor
lint
lit Pass 2 more variables to lit tests. 2015-06-23 20:57:26 +00:00
llvm-build
llvm-lit
Misc
not
PerfectShuffle
release test-release.sh: Remove the InstallDir parameter from configure_llvmCore 2015-07-14 20:15:15 +00:00
TableGen [TableGen] Improve decoding options for non-orthogonal instructions 2015-07-15 08:04:27 +00:00
Target/ARM
testgen
textmate
unittest Make UnitTestMain/TestMain.cpp free from llvm/Config/config.h. 2015-07-06 23:51:40 +00:00
valgrind
vim [vim] Update the syntax to mark REQUIRES lines and not talk about 2015-07-15 01:48:40 +00:00
yaml-bench YAML: Implement block scalar parsing. 2015-05-13 23:10:51 +00:00
bisect
check-each-file
clang-parse-diagnostics-file
codegen-diff
countloc.sh
create_ladder_graph.py
DSAclean.py
DSAextract.py
findmisopt
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findsym.pl
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lldbDataFormatters.py
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llvm.grm
llvm.natvis
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makellvm
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sort_includes.py Add polly support to sort_includes.py 2015-05-09 09:08:56 +00:00
test_debuginfo.pl
update_llc_test_checks.py
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