mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 03:30:28 +00:00
ea14085be5
Before the patch we took advantage of the fact that the compare and branch are glued together in the selection DAG and fused them together (where possible) while emitting them. This seemed to work well in practice. However, fusing the compare so early makes it harder to remove redundant compares in cases where CC already has a suitable value. This patch therefore uses the peephole analyzeCompare/optimizeCompareInstr pair of functions instead. No behavioral change intended, but it paves the way for a later patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187116 91177308-0d34-0410-b5e6-96231b3b80d8
1326 lines
46 KiB
TableGen
1326 lines
46 KiB
TableGen
//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Basic SystemZ instruction definition
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//===----------------------------------------------------------------------===//
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class InstSystemZ<int size, dag outs, dag ins, string asmstr,
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list<dag> pattern> : Instruction {
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let Namespace = "SystemZ";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let Size = size;
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let Pattern = pattern;
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let AsmString = asmstr;
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// Some instructions come in pairs, one having a 12-bit displacement
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// and the other having a 20-bit displacement. Both instructions in
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// the pair have the same DispKey and their DispSizes are "12" and "20"
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// respectively.
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string DispKey = "";
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string DispSize = "none";
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// Many register-based <INSN>R instructions have a memory-based <INSN>
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// counterpart. OpKey uniquely identifies <INSN>, while OpType is
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// "reg" for <INSN>R and "mem" for <INSN>.
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string OpKey = "";
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string OpType = "none";
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// Many distinct-operands instructions have older 2-operand equivalents.
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// NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
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// with NumOpsValue being "2" or "3" as appropriate.
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string NumOpsKey = "";
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string NumOpsValue = "none";
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// True if this instruction is a simple D(X,B) load of a register
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// (with no sign or zero extension).
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bit SimpleBDXLoad = 0;
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// True if this instruction is a simple D(X,B) store of a register
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// (with no truncation).
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bit SimpleBDXStore = 0;
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// True if this instruction has a 20-bit displacement field.
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bit Has20BitOffset = 0;
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// True if addresses in this instruction have an index register.
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bit HasIndex = 0;
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// True if this is a 128-bit pseudo instruction that combines two 64-bit
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// operations.
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bit Is128Bit = 0;
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// The access size of all memory operands in bytes, or 0 if not known.
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bits<5> AccessBytes = 0;
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let TSFlags{0} = SimpleBDXLoad;
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let TSFlags{1} = SimpleBDXStore;
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let TSFlags{2} = Has20BitOffset;
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let TSFlags{3} = HasIndex;
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let TSFlags{4} = Is128Bit;
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let TSFlags{9-5} = AccessBytes;
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}
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//===----------------------------------------------------------------------===//
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// Mappings between instructions
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//===----------------------------------------------------------------------===//
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// Return the version of an instruction that has an unsigned 12-bit
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// displacement.
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def getDisp12Opcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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let RowFields = ["DispKey"];
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let ColFields = ["DispSize"];
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let KeyCol = ["20"];
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let ValueCols = [["12"]];
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}
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// Return the version of an instruction that has a signed 20-bit displacement.
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def getDisp20Opcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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let RowFields = ["DispKey"];
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let ColFields = ["DispSize"];
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let KeyCol = ["12"];
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let ValueCols = [["20"]];
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}
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// Return the memory form of a register instruction.
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def getMemOpcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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let RowFields = ["OpKey"];
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let ColFields = ["OpType"];
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let KeyCol = ["reg"];
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let ValueCols = [["mem"]];
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}
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// Return the 3-operand form of a 2-operand instruction.
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def getThreeOperandOpcode : InstrMapping {
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let FilterClass = "InstSystemZ";
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let RowFields = ["NumOpsKey"];
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let ColFields = ["NumOpsValue"];
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let KeyCol = ["2"];
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let ValueCols = [["3"]];
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}
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//===----------------------------------------------------------------------===//
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// Instruction formats
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//===----------------------------------------------------------------------===//
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//
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// Formats are specified using operand field declarations of the form:
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//
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// bits<4> Rn : register input or output for operand n
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// bits<m> In : immediate value of width m for operand n
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// bits<4> BDn : address operand n, which has a base and a displacement
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// bits<m> XBDn : address operand n, which has an index, a base and a
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// displacement
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// bits<4> Xn : index register for address operand n
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// bits<4> Mn : mode value for operand n
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//
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// The operand numbers ("n" in the list above) follow the architecture manual.
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// Assembly operands sometimes have a different order; in particular, R3 often
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// is often written between operands 1 and 2.
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//
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//===----------------------------------------------------------------------===//
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class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<4> R1;
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bits<16> I2;
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let Inst{31-24} = op{11-4};
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let Inst{23-20} = R1;
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let Inst{19-16} = op{3-0};
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let Inst{15-0} = I2;
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}
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class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<4> R2;
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bits<4> M3;
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bits<16> RI4;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = R2;
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let Inst{31-16} = RI4;
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let Inst{15-12} = M3;
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let Inst{11-8} = 0;
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let Inst{7-0} = op{7-0};
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}
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class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<8> I2;
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bits<4> M3;
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bits<16> RI4;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = M3;
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let Inst{31-16} = RI4;
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let Inst{15-8} = I2;
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let Inst{7-0} = op{7-0};
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}
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class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<4> R3;
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bits<16> I2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = R3;
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let Inst{31-16} = I2;
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let Inst{15-8} = 0;
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let Inst{7-0} = op{7-0};
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}
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class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<4> R2;
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bits<8> I3;
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bits<8> I4;
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bits<8> I5;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = R2;
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let Inst{31-24} = I3;
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let Inst{23-16} = I4;
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let Inst{15-8} = I5;
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let Inst{7-0} = op{7-0};
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}
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class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<32> I2;
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let Inst{47-40} = op{11-4};
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let Inst{39-36} = R1;
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let Inst{35-32} = op{3-0};
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let Inst{31-0} = I2;
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}
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class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<2, outs, ins, asmstr, pattern> {
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field bits<16> Inst;
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field bits<16> SoftFail = 0;
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bits<4> R1;
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bits<4> R2;
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let Inst{15-8} = op;
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let Inst{7-4} = R1;
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let Inst{3-0} = R2;
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}
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class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<4> R1;
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bits<4> R3;
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bits<4> R2;
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let Inst{31-16} = op;
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let Inst{15-12} = R1;
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let Inst{11-8} = 0;
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let Inst{7-4} = R3;
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let Inst{3-0} = R2;
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}
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class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<4> R1;
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bits<4> R2;
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let Inst{31-16} = op;
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let Inst{15-8} = 0;
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let Inst{7-4} = R1;
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let Inst{3-0} = R2;
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}
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class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<4> R1;
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bits<4> R2;
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bits<4> R3;
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let Inst{31-16} = op;
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let Inst{15-12} = R3;
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let Inst{11-8} = 0;
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let Inst{7-4} = R1;
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let Inst{3-0} = R2;
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}
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class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<4> R1;
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bits<20> XBD2;
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let Inst{31-24} = op;
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let Inst{23-20} = R1;
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let Inst{19-0} = XBD2;
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let HasIndex = 1;
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}
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class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<20> XBD2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-16} = XBD2;
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let Inst{15-8} = 0;
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let Inst{7-0} = op{7-0};
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let HasIndex = 1;
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}
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class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<4> R3;
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bits<20> XBD2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R3;
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let Inst{35-16} = XBD2;
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let Inst{15-12} = R1;
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let Inst{11-8} = 0;
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let Inst{7-0} = op{7-0};
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let HasIndex = 1;
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}
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class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<28> XBD2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-8} = XBD2;
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let Inst{7-0} = op{7-0};
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let Has20BitOffset = 1;
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let HasIndex = 1;
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}
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class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<4> R1;
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bits<4> R3;
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bits<16> BD2;
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let Inst{31-24} = op;
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let Inst{23-20} = R1;
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let Inst{19-16} = R3;
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let Inst{15-0} = BD2;
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}
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class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<4> R3;
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bits<24> BD2;
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let Inst{47-40} = op{15-8};
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let Inst{39-36} = R1;
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let Inst{35-32} = R3;
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let Inst{31-8} = BD2;
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let Inst{7-0} = op{7-0};
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let Has20BitOffset = 1;
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}
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class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<4, outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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bits<16> BD1;
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bits<8> I2;
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let Inst{31-24} = op;
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let Inst{23-16} = I2;
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let Inst{15-0} = BD1;
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}
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class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<16> BD1;
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bits<16> I2;
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let Inst{47-32} = op;
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let Inst{31-16} = BD1;
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let Inst{15-0} = I2;
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}
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class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<24> BD1;
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bits<8> I2;
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let Inst{47-40} = op{15-8};
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let Inst{39-32} = I2;
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let Inst{31-8} = BD1;
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let Inst{7-0} = op{7-0};
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let Has20BitOffset = 1;
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}
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class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<24> BDL1;
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bits<16> BD2;
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let Inst{47-40} = op;
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let Inst{39-16} = BDL1;
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let Inst{15-0} = BD2;
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}
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//===----------------------------------------------------------------------===//
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// Instruction definitions with semantics
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//===----------------------------------------------------------------------===//
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//
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// These classes have the form [Cond]<Category><Format>, where <Format> is one
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// of the formats defined above and where <Category> describes the inputs
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// and outputs. "Cond" is used if the instruction is conditional,
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// in which case the 4-bit condition-code mask is added as a final operand.
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// <Category> can be one of:
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//
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// Inherent:
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// One register output operand and no input operands.
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//
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// Store:
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// One register or immediate input operand and one address input operand.
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// The instruction stores the first operand to the address.
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//
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// This category is used for both pure and truncating stores.
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//
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// LoadMultiple:
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// One address input operand and two explicit output operands.
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// The instruction loads a range of registers from the address,
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// with the explicit operands giving the first and last register
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// to load. Other loaded registers are added as implicit definitions.
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//
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// StoreMultiple:
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// Two explicit input register operands and an address operand.
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// The instruction stores a range of registers to the address,
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// with the explicit operands giving the first and last register
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// to store. Other stored registers are added as implicit uses.
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//
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// Unary:
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// One register output operand and one input operand. The input
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// operand may be a register, immediate or memory.
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//
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// Binary:
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// One register output operand and two input operands. The first
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// input operand is always a register and he second may be a register,
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// immediate or memory.
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//
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// Shift:
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// One register output operand and two input operands. The first
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// input operand is a register and the second has the same form as
|
|
// an address (although it isn't actually used to address memory).
|
|
//
|
|
// Compare:
|
|
// Two input operands. The first operand is always a register,
|
|
// the second may be a register, immediate or memory.
|
|
//
|
|
// Ternary:
|
|
// One register output operand and three register input operands.
|
|
//
|
|
// CmpSwap:
|
|
// One output operand and three input operands. The first two
|
|
// operands are registers and the third is an address. The instruction
|
|
// both reads from and writes to the address.
|
|
//
|
|
// RotateSelect:
|
|
// One output operand and five input operands. The first two operands
|
|
// are registers and the other three are immediates.
|
|
//
|
|
// The format determines which input operands are tied to output operands,
|
|
// and also determines the shape of any address operand.
|
|
//
|
|
// Multiclasses of the form <Category><Format>Pair define two instructions,
|
|
// one with <Category><Format> and one with <Category><Format>Y. The name
|
|
// of the first instruction has no suffix, the name of the second has
|
|
// an extra "y".
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
|
dag src>
|
|
: InstRRE<opcode, (outs cls:$R1), (ins),
|
|
mnemonic#"r\t$R1",
|
|
[(set cls:$R1, src)]> {
|
|
let R2 = 0;
|
|
}
|
|
|
|
class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
|
: InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
|
|
mnemonic#"\t$R1, $R3, $BD2", []> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls>
|
|
: InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(operator cls:$R1, pcrel32:$I2)]> {
|
|
let mayStore = 1;
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
// complex.
|
|
let AddedComplexity = 7;
|
|
}
|
|
|
|
class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, bits<5> bytes,
|
|
AddressingMode mode = bdxaddr12only>
|
|
: InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(operator cls:$R1, mode:$XBD2)]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let mayStore = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, bits<5> bytes,
|
|
AddressingMode mode = bdxaddr20only>
|
|
: InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(operator cls:$R1, mode:$XBD2)]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let mayStore = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
bits<5> bytes> {
|
|
let DispKey = mnemonic ## #cls in {
|
|
let DispSize = "12" in
|
|
def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
|
|
let DispSize = "20" in
|
|
def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
|
|
bdxaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
|
: InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2),
|
|
mnemonic#"\t$R1, $R3, $BD2", []> {
|
|
let mayStore = 1;
|
|
}
|
|
|
|
class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
Immediate imm, AddressingMode mode = bdaddr12only>
|
|
: InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator imm:$I2, mode:$BD1)]> {
|
|
let mayStore = 1;
|
|
}
|
|
|
|
class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
Immediate imm, AddressingMode mode = bdaddr20only>
|
|
: InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator imm:$I2, mode:$BD1)]> {
|
|
let mayStore = 1;
|
|
}
|
|
|
|
class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
Immediate imm>
|
|
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator imm:$I2, bdaddr12only:$BD1)]> {
|
|
let mayStore = 1;
|
|
}
|
|
|
|
multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
|
|
SDPatternOperator operator, Immediate imm> {
|
|
let DispKey = mnemonic in {
|
|
let DispSize = "12" in
|
|
def "" : StoreSI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
|
|
let DispSize = "20" in
|
|
def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class CondStoreRSY<string mnemonic, bits<16> opcode,
|
|
RegisterOperand cls, bits<5> bytes,
|
|
AddressingMode mode = bdaddr20only>
|
|
: InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$R3),
|
|
mnemonic#"$R3\t$R1, $BD2", []>,
|
|
Requires<[FeatureLoadStoreOnCond]> {
|
|
let mayStore = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
// Like CondStoreRSY, but used for the raw assembly form. The condition-code
|
|
// mask is the third operand rather than being part of the mnemonic.
|
|
class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
|
|
RegisterOperand cls, bits<5> bytes,
|
|
AddressingMode mode = bdaddr20only>
|
|
: InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, uimm8zx4:$R3),
|
|
mnemonic#"\t$R1, $BD2, $R3", []>,
|
|
Requires<[FeatureLoadStoreOnCond]> {
|
|
let mayStore = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
// Like CondStoreRSY, but with a fixed CC mask.
|
|
class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
|
|
RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
|
|
AddressingMode mode = bdaddr20only>
|
|
: InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2),
|
|
mnemonic#"\t$R1, $BD2", []>,
|
|
Requires<[FeatureLoadStoreOnCond]> {
|
|
let mayStore = 1;
|
|
let AccessBytes = bytes;
|
|
let R3 = ccmask;
|
|
}
|
|
|
|
class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
|
|
mnemonic#"r\t$R1, $R2",
|
|
[(set cls1:$R1, (operator cls2:$R2))]> {
|
|
let OpKey = mnemonic ## cls1;
|
|
let OpType = "reg";
|
|
}
|
|
|
|
class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
|
|
mnemonic#"r\t$R1, $R2",
|
|
[(set cls1:$R1, (operator cls2:$R2))]> {
|
|
let OpKey = mnemonic ## cls1;
|
|
let OpType = "reg";
|
|
}
|
|
|
|
class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
RegisterOperand cls2>
|
|
: InstRRF<opcode, (outs cls1:$R1), (ins uimm8zx4:$R3, cls2:$R2),
|
|
mnemonic#"r\t$R1, $R3, $R2", []> {
|
|
let OpKey = mnemonic ## cls1;
|
|
let OpType = "reg";
|
|
}
|
|
|
|
// These instructions are generated by if conversion. The old value of R1
|
|
// is added as an implicit use.
|
|
class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
RegisterOperand cls2>
|
|
: InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$R3),
|
|
mnemonic#"r$R3\t$R1, $R2", []>,
|
|
Requires<[FeatureLoadStoreOnCond]>;
|
|
|
|
// Like CondUnaryRRF, but used for the raw assembly form. The condition-code
|
|
// mask is the third operand rather than being part of the mnemonic.
|
|
class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
RegisterOperand cls2>
|
|
: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, uimm8zx4:$R3),
|
|
mnemonic#"r\t$R1, $R2, $R3", []>,
|
|
Requires<[FeatureLoadStoreOnCond]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
// Like CondUnaryRRF, but with a fixed CC mask.
|
|
class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
RegisterOperand cls2, bits<4> ccmask>
|
|
: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
|
|
mnemonic#"\t$R1, $R2", []>,
|
|
Requires<[FeatureLoadStoreOnCond]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let R3 = ccmask;
|
|
}
|
|
|
|
class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator imm:$I2))]>;
|
|
|
|
class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator imm:$I2))]>;
|
|
|
|
class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls>
|
|
: InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator pcrel32:$I2))]> {
|
|
let mayLoad = 1;
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
// complex.
|
|
let AddedComplexity = 7;
|
|
}
|
|
|
|
class CondUnaryRSY<string mnemonic, bits<16> opcode,
|
|
RegisterOperand cls, bits<5> bytes,
|
|
AddressingMode mode = bdaddr20only>
|
|
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, cond4:$R3),
|
|
mnemonic#"$R3\t$R1, $BD2", []>,
|
|
Requires<[FeatureLoadStoreOnCond]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
// Like CondUnaryRSY, but used for the raw assembly form. The condition-code
|
|
// mask is the third operand rather than being part of the mnemonic.
|
|
class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
|
|
RegisterOperand cls, bits<5> bytes,
|
|
AddressingMode mode = bdaddr20only>
|
|
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, uimm8zx4:$R3),
|
|
mnemonic#"\t$R1, $BD2, $R3", []>,
|
|
Requires<[FeatureLoadStoreOnCond]> {
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
// Like CondUnaryRSY, but with a fixed CC mask.
|
|
class FixedCondUnaryRSY<string mnemonic, bits<16> opcode,
|
|
RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
|
|
AddressingMode mode = bdaddr20only>
|
|
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
|
|
mnemonic#"\t$R1, $BD2", []>,
|
|
Requires<[FeatureLoadStoreOnCond]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let R3 = ccmask;
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, bits<5> bytes,
|
|
AddressingMode mode = bdxaddr12only>
|
|
: InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator mode:$XBD2))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, bits<5> bytes>
|
|
: InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, bits<5> bytes,
|
|
AddressingMode mode = bdxaddr20only>
|
|
: InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator mode:$XBD2))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
bits<5> bytes> {
|
|
let DispKey = mnemonic ## #cls in {
|
|
let DispSize = "12" in
|
|
def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
|
|
let DispSize = "20" in
|
|
def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
|
|
bdxaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
|
|
mnemonic#"r\t$R1, $R2",
|
|
[(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
|
|
let OpKey = mnemonic ## cls1;
|
|
let OpType = "reg";
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
|
|
mnemonic#"r\t$R1, $R2",
|
|
[(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
|
|
let OpKey = mnemonic ## cls1;
|
|
let OpType = "reg";
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2),
|
|
mnemonic#"r\t$R1, $R3, $R2",
|
|
[(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]> {
|
|
let OpKey = mnemonic ## cls1;
|
|
let OpType = "reg";
|
|
}
|
|
|
|
class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
|
|
mnemonic#"rk\t$R1, $R2, $R3",
|
|
[(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]>;
|
|
|
|
multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
|
|
SDPatternOperator operator, RegisterOperand cls1,
|
|
RegisterOperand cls2> {
|
|
let NumOpsKey = mnemonic in {
|
|
let NumOpsValue = "3" in
|
|
def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
|
|
Requires<[FeatureDistinctOps]>;
|
|
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
|
|
def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
|
|
}
|
|
}
|
|
|
|
multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
|
|
SDPatternOperator operator, RegisterOperand cls1,
|
|
RegisterOperand cls2> {
|
|
let NumOpsKey = mnemonic in {
|
|
let NumOpsValue = "3" in
|
|
def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
|
|
Requires<[FeatureDistinctOps]>;
|
|
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
|
|
def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
|
|
}
|
|
}
|
|
|
|
class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
|
|
mnemonic#"\t$R1, $R3, $I2",
|
|
[(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
|
|
|
|
multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
Immediate imm> {
|
|
let NumOpsKey = mnemonic in {
|
|
let NumOpsValue = "3" in
|
|
def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
|
|
Requires<[FeatureDistinctOps]>;
|
|
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
|
|
def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
|
|
}
|
|
}
|
|
|
|
class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
|
AddressingMode mode = bdxaddr12only>
|
|
: InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
|
|
: InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator cls:$R1src,
|
|
(load bdxaddr12only:$XBD2)))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
|
AddressingMode mode = bdxaddr20only>
|
|
: InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
SDPatternOperator load, bits<5> bytes> {
|
|
let DispKey = mnemonic ## #cls in {
|
|
let DispSize = "12" in
|
|
def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
|
|
bdxaddr12pair>;
|
|
let DispSize = "20" in
|
|
def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
|
|
bdxaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
Operand imm, AddressingMode mode = bdaddr12only>
|
|
: InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
}
|
|
|
|
class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
Operand imm, AddressingMode mode = bdaddr20only>
|
|
: InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
}
|
|
|
|
multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
|
|
bits<16> siyOpcode, SDPatternOperator operator,
|
|
Operand imm> {
|
|
let DispKey = mnemonic ## #cls in {
|
|
let DispSize = "12" in
|
|
def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
|
|
let DispSize = "20" in
|
|
def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class ShiftRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls>
|
|
: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
|
|
mnemonic#"\t$R1, $BD2",
|
|
[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
|
|
let R3 = 0;
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class ShiftRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls>
|
|
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
[(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
|
|
|
|
multiclass ShiftRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
|
|
SDPatternOperator operator, RegisterOperand cls> {
|
|
let NumOpsKey = mnemonic in {
|
|
let NumOpsValue = "3" in
|
|
def K : ShiftRSY<mnemonic##"k", opcode2, null_frag, cls>,
|
|
Requires<[FeatureDistinctOps]>;
|
|
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
|
|
def "" : ShiftRS<mnemonic, opcode1, operator, cls>;
|
|
}
|
|
}
|
|
|
|
class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
|
|
mnemonic#"r\t$R1, $R2",
|
|
[(operator cls1:$R1, cls2:$R2)]> {
|
|
let OpKey = mnemonic ## cls1;
|
|
let OpType = "reg";
|
|
let isCompare = 1;
|
|
}
|
|
|
|
class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls1, RegisterOperand cls2>
|
|
: InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
|
|
mnemonic#"r\t$R1, $R2",
|
|
[(operator cls1:$R1, cls2:$R2)]> {
|
|
let OpKey = mnemonic ## cls1;
|
|
let OpType = "reg";
|
|
let isCompare = 1;
|
|
}
|
|
|
|
class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(operator cls:$R1, imm:$I2)]> {
|
|
let isCompare = 1;
|
|
}
|
|
|
|
class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, Immediate imm>
|
|
: InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(operator cls:$R1, imm:$I2)]> {
|
|
let isCompare = 1;
|
|
}
|
|
|
|
class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load>
|
|
: InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
|
|
mnemonic#"\t$R1, $I2",
|
|
[(operator cls:$R1, (load pcrel32:$I2))]> {
|
|
let isCompare = 1;
|
|
let mayLoad = 1;
|
|
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
|
// However, BDXs have two extra operands and are therefore 6 units more
|
|
// complex.
|
|
let AddedComplexity = 7;
|
|
}
|
|
|
|
class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
|
AddressingMode mode = bdxaddr12only>
|
|
: InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(operator cls:$R1, (load mode:$XBD2))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let isCompare = 1;
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
|
|
: InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let isCompare = 1;
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
|
|
AddressingMode mode = bdxaddr20only>
|
|
: InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
|
|
mnemonic#"\t$R1, $XBD2",
|
|
[(operator cls:$R1, (load mode:$XBD2))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let isCompare = 1;
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
|
SDPatternOperator operator, RegisterOperand cls,
|
|
SDPatternOperator load, bits<5> bytes> {
|
|
let DispKey = mnemonic ## #cls in {
|
|
let DispSize = "12" in
|
|
def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
|
|
load, bytes, bdxaddr12pair>;
|
|
let DispSize = "20" in
|
|
def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
|
|
load, bytes, bdxaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
SDPatternOperator load, Immediate imm,
|
|
AddressingMode mode = bdaddr12only>
|
|
: InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator (load mode:$BD1), imm:$I2)]> {
|
|
let isCompare = 1;
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
SDPatternOperator load, Immediate imm>
|
|
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator (load bdaddr12only:$BD1), imm:$I2)]> {
|
|
let isCompare = 1;
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
SDPatternOperator load, Immediate imm,
|
|
AddressingMode mode = bdaddr20only>
|
|
: InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
|
|
mnemonic#"\t$BD1, $I2",
|
|
[(operator (load mode:$BD1), imm:$I2)]> {
|
|
let isCompare = 1;
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
|
|
SDPatternOperator operator, SDPatternOperator load,
|
|
Immediate imm> {
|
|
let DispKey = mnemonic in {
|
|
let DispSize = "12" in
|
|
def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
|
|
let DispSize = "20" in
|
|
def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
|
|
bdaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class TernaryRRD<string mnemonic, bits<16> opcode,
|
|
SDPatternOperator operator, RegisterOperand cls>
|
|
: InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
|
|
mnemonic#"r\t$R1, $R3, $R2",
|
|
[(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "reg";
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
|
|
: InstRXF<opcode, (outs cls:$R1),
|
|
(ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
|
|
mnemonic#"\t$R1, $R3, $XBD2",
|
|
[(set cls:$R1, (operator cls:$R1src, cls:$R3,
|
|
(load bdxaddr12only:$XBD2)))]> {
|
|
let OpKey = mnemonic ## cls;
|
|
let OpType = "mem";
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
let AccessBytes = bytes;
|
|
}
|
|
|
|
class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, AddressingMode mode = bdaddr12only>
|
|
: InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
}
|
|
|
|
class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
|
RegisterOperand cls, AddressingMode mode = bdaddr20only>
|
|
: InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
|
|
mnemonic#"\t$R1, $R3, $BD2",
|
|
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
}
|
|
|
|
multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
|
|
SDPatternOperator operator, RegisterOperand cls> {
|
|
let DispKey = mnemonic ## #cls in {
|
|
let DispSize = "12" in
|
|
def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
|
|
let DispSize = "20" in
|
|
def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
|
|
}
|
|
}
|
|
|
|
class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
|
RegisterOperand cls2>
|
|
: InstRIEf<opcode, (outs cls1:$R1),
|
|
(ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5),
|
|
mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
|
|
let Constraints = "$R1 = $R1src";
|
|
let DisableEncoding = "$R1src";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo instructions
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// Convenience instructions that get lowered to real instructions
|
|
// by either SystemZTargetLowering::EmitInstrWithCustomInserter()
|
|
// or SystemZInstrInfo::expandPostRAPseudo().
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class Pseudo<dag outs, dag ins, list<dag> pattern>
|
|
: InstSystemZ<0, outs, ins, "", pattern> {
|
|
let isPseudo = 1;
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
|
|
// the value of the PSW's 2-bit condition code field.
|
|
class SelectWrapper<RegisterOperand cls>
|
|
: Pseudo<(outs cls:$dst), (ins cls:$src1, cls:$src2, i8imm:$cc),
|
|
[(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, imm:$cc))]> {
|
|
let usesCustomInserter = 1;
|
|
// Although the instructions used by these nodes do not in themselves
|
|
// change CC, the insertion requires new blocks, and CC cannot be live
|
|
// across them.
|
|
let Defs = [CC];
|
|
let Uses = [CC];
|
|
}
|
|
|
|
// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
|
|
multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
|
|
SDPatternOperator load, AddressingMode mode> {
|
|
let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
|
|
def "" : Pseudo<(outs), (ins cls:$new, mode:$addr, uimm8zx4:$cc),
|
|
[(store (z_select_ccmask cls:$new, (load mode:$addr),
|
|
uimm8zx4:$cc), mode:$addr)]>;
|
|
def Inv : Pseudo<(outs), (ins cls:$new, mode:$addr, uimm8zx4:$cc),
|
|
[(store (z_select_ccmask (load mode:$addr), cls:$new,
|
|
uimm8zx4:$cc), mode:$addr)]>;
|
|
}
|
|
}
|
|
|
|
// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
|
|
// describe the second (non-memory) operand.
|
|
class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
|
|
dag pat, DAGOperand operand>
|
|
: Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
|
|
[(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
|
|
let Defs = [CC];
|
|
let Has20BitOffset = 1;
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
let usesCustomInserter = 1;
|
|
}
|
|
|
|
// Specializations of AtomicLoadWBinary.
|
|
class AtomicLoadBinaryReg32<SDPatternOperator operator>
|
|
: AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
|
|
class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
|
|
: AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
|
|
class AtomicLoadBinaryReg64<SDPatternOperator operator>
|
|
: AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
|
|
class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
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: AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
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// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
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// describe the second (non-memory) operand.
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class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
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DAGOperand operand>
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: Pseudo<(outs GR32:$dst),
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(ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
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ADDR32:$negbitshift, uimm32:$bitsize),
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[(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
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ADDR32:$negbitshift, uimm32:$bitsize))]> {
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let Defs = [CC];
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let Has20BitOffset = 1;
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let mayLoad = 1;
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let mayStore = 1;
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let usesCustomInserter = 1;
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}
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// Specializations of AtomicLoadWBinary.
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class AtomicLoadWBinaryReg<SDPatternOperator operator>
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: AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
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class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
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: AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
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