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llvm-6502/lib/Target/XCore
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Preston Gurd 6a8c7bf8e7 This patch fixes a problem which arose when using the Post-RA scheduler 
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.

This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.

This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.

The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().  

It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.

It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.

Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.

Patch by Andy Zhang!

Thanks to Jakob and Anton for their reviews.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23 21:39:35 +00:00
..
MCTargetDesc Prune some includes 2012-03-27 07:54:11 +00:00
TargetInfo
CMakeLists.txt
LLVMBuild.txt
Makefile
README.txt
XCore.h
XCore.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreAsmPrinter.cpp
XCoreCallingConv.td
XCoreFrameLowering.cpp Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. 2012-04-20 07:30:17 +00:00
XCoreFrameLowering.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreInstrFormats.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreInstrInfo.cpp Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
XCoreInstrInfo.h Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
XCoreInstrInfo.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreISelDAGToDAG.cpp
XCoreISelLowering.cpp Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. 2012-04-20 07:30:17 +00:00
XCoreISelLowering.h Always compute all the bits in ComputeMaskedBits. 2012-04-04 12:51:34 +00:00
XCoreMachineFunctionInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreMachineFunctionInfo.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreRegisterInfo.cpp This patch fixes a problem which arose when using the Post-RA scheduler 2012-04-23 21:39:35 +00:00
XCoreRegisterInfo.h This patch fixes a problem which arose when using the Post-RA scheduler 2012-04-23 21:39:35 +00:00
XCoreRegisterInfo.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreSelectionDAGInfo.cpp
XCoreSelectionDAGInfo.h
XCoreSubtarget.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreSubtarget.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreTargetMachine.cpp TargetPassConfig: confine the MC configuration to TargetMachine. 2012-02-04 02:56:59 +00:00
XCoreTargetMachine.h Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
XCoreTargetObjectFile.cpp
XCoreTargetObjectFile.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00

README.txt 

To-do
-----

* Instruction encodings
* Tailcalls
* Investigate loop alignment
* Add builtins