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llvm-6502/test/CodeGen/ARM/fast-isel-conversion.ll
JF Bastien fe532ad6d6 Enable FastISel on ARM for Linux and NaCl, not MCJIT 
This is a resubmit of r182877, which was reverted because it broken
MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only
enabled for iOS. I've CC'ed people from the original review and revert.

FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl, but not MCJIT.

Thumb2 support needs a bit more work, mainly around register class
restrictions.

The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.

The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.

The test changes are straightforward, similar to:
  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.

I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0
and all the tests pass. All the tests also pass on x86 make check-all. I
also re-ran the check-all tests that failed on ARM, and they all seem to
pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183966 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-14 02:49:43 +00:00

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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; Test sitofp
define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
entry:
; ARM: sitofp_single_i32
; ARM: vmov s0, r0
; ARM: vcvt.f32.s32 s0, s0
; THUMB: sitofp_single_i32
; THUMB: vmov s0, r0
; THUMB: vcvt.f32.s32 s0, s0
%b.addr = alloca float, align 4
%conv = sitofp i32 %a to float
store float %conv, float* %b.addr, align 4
ret void
}
define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
entry:
; ARM: sitofp_single_i16
; ARM: sxth r0, r0
; ARM: vmov s0, r0
; ARM: vcvt.f32.s32 s0, s0
; THUMB: sitofp_single_i16
; THUMB: sxth r0, r0
; THUMB: vmov s0, r0
; THUMB: vcvt.f32.s32 s0, s0
%b.addr = alloca float, align 4
%conv = sitofp i16 %a to float
store float %conv, float* %b.addr, align 4
ret void
}
define void @sitofp_single_i8(i8 %a) nounwind ssp {
entry:
; ARM: sitofp_single_i8
; ARM: sxtb r0, r0
; ARM: vmov s0, r0
; ARM: vcvt.f32.s32 s0, s0
; THUMB: sitofp_single_i8
; THUMB: sxtb r0, r0
; THUMB: vmov s0, r0
; THUMB: vcvt.f32.s32 s0, s0
%b.addr = alloca float, align 4
%conv = sitofp i8 %a to float
store float %conv, float* %b.addr, align 4
ret void
}
define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
entry:
; ARM: sitofp_double_i32
; ARM: vmov s0, r0
; ARM: vcvt.f64.s32 d16, s0
; THUMB: sitofp_double_i32
; THUMB: vmov s0, r0
; THUMB: vcvt.f64.s32 d16, s0
%b.addr = alloca double, align 8
%conv = sitofp i32 %a to double
store double %conv, double* %b.addr, align 8
ret void
}
define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
entry:
; ARM: sitofp_double_i16
; ARM: sxth r0, r0
; ARM: vmov s0, r0
; ARM: vcvt.f64.s32 d16, s0
; THUMB: sitofp_double_i16
; THUMB: sxth r0, r0
; THUMB: vmov s0, r0
; THUMB: vcvt.f64.s32 d16, s0
%b.addr = alloca double, align 8
%conv = sitofp i16 %a to double
store double %conv, double* %b.addr, align 8
ret void
}
define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
entry:
; ARM: sitofp_double_i8
; ARM: sxtb r0, r0
; ARM: vmov s0, r0
; ARM: vcvt.f64.s32 d16, s0
; THUMB: sitofp_double_i8
; THUMB: sxtb r0, r0
; THUMB: vmov s0, r0
; THUMB: vcvt.f64.s32 d16, s0
%b.addr = alloca double, align 8
%conv = sitofp i8 %a to double
store double %conv, double* %b.addr, align 8
ret void
}
; Test uitofp
define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
entry:
; ARM: uitofp_single_i32
; ARM: vmov s0, r0
; ARM: vcvt.f32.u32 s0, s0
; THUMB: uitofp_single_i32
; THUMB: vmov s0, r0
; THUMB: vcvt.f32.u32 s0, s0
%b.addr = alloca float, align 4
%conv = uitofp i32 %a to float
store float %conv, float* %b.addr, align 4
ret void
}
define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
entry:
; ARM: uitofp_single_i16
; ARM: uxth r0, r0
; ARM: vmov s0, r0
; ARM: vcvt.f32.u32 s0, s0
; THUMB: uitofp_single_i16
; THUMB: uxth r0, r0
; THUMB: vmov s0, r0
; THUMB: vcvt.f32.u32 s0, s0
%b.addr = alloca float, align 4
%conv = uitofp i16 %a to float
store float %conv, float* %b.addr, align 4
ret void
}
define void @uitofp_single_i8(i8 %a) nounwind ssp {
entry:
; ARM: uitofp_single_i8
; ARM: and r0, r0, #255
; ARM: vmov s0, r0
; ARM: vcvt.f32.u32 s0, s0
; THUMB: uitofp_single_i8
; THUMB: and r0, r0, #255
; THUMB: vmov s0, r0
; THUMB: vcvt.f32.u32 s0, s0
%b.addr = alloca float, align 4
%conv = uitofp i8 %a to float
store float %conv, float* %b.addr, align 4
ret void
}
define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
entry:
; ARM: uitofp_double_i32
; ARM: vmov s0, r0
; ARM: vcvt.f64.u32 d16, s0
; THUMB: uitofp_double_i32
; THUMB: vmov s0, r0
; THUMB: vcvt.f64.u32 d16, s0
%b.addr = alloca double, align 8
%conv = uitofp i32 %a to double
store double %conv, double* %b.addr, align 8
ret void
}
define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
entry:
; ARM: uitofp_double_i16
; ARM: uxth r0, r0
; ARM: vmov s0, r0
; ARM: vcvt.f64.u32 d16, s0
; THUMB: uitofp_double_i16
; THUMB: uxth r0, r0
; THUMB: vmov s0, r0
; THUMB: vcvt.f64.u32 d16, s0
%b.addr = alloca double, align 8
%conv = uitofp i16 %a to double
store double %conv, double* %b.addr, align 8
ret void
}
define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
entry:
; ARM: uitofp_double_i8
; ARM: and r0, r0, #255
; ARM: vmov s0, r0
; ARM: vcvt.f64.u32 d16, s0
; THUMB: uitofp_double_i8
; THUMB: and r0, r0, #255
; THUMB: vmov s0, r0
; THUMB: vcvt.f64.u32 d16, s0
%b.addr = alloca double, align 8
%conv = uitofp i8 %a to double
store double %conv, double* %b.addr, align 8
ret void
}
; Test fptosi
define void @fptosi_float(float %a) nounwind ssp {
entry:
; ARM: fptosi_float
; ARM: vcvt.s32.f32 s0, s0
; THUMB: fptosi_float
; THUMB: vcvt.s32.f32 s0, s0
%b.addr = alloca i32, align 4
%conv = fptosi float %a to i32
store i32 %conv, i32* %b.addr, align 4
ret void
}
define void @fptosi_double(double %a) nounwind ssp {
entry:
; ARM: fptosi_double
; ARM: vcvt.s32.f64 s0, d16
; THUMB: fptosi_double
; THUMB: vcvt.s32.f64 s0, d16
%b.addr = alloca i32, align 8
%conv = fptosi double %a to i32
store i32 %conv, i32* %b.addr, align 8
ret void
}
; Test fptoui
define void @fptoui_float(float %a) nounwind ssp {
entry:
; ARM: fptoui_float
; ARM: vcvt.u32.f32 s0, s0
; THUMB: fptoui_float
; THUMB: vcvt.u32.f32 s0, s0
%b.addr = alloca i32, align 4
%conv = fptoui float %a to i32
store i32 %conv, i32* %b.addr, align 4
ret void
}
define void @fptoui_double(double %a) nounwind ssp {
entry:
; ARM: fptoui_double
; ARM: vcvt.u32.f64 s0, d16
; THUMB: fptoui_double
; THUMB: vcvt.u32.f64 s0, d16
%b.addr = alloca i32, align 8
%conv = fptoui double %a to i32
store i32 %conv, i32* %b.addr, align 8
ret void
}
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