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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
295 lines
11 KiB
C++
295 lines
11 KiB
C++
//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LLVMTargetMachine class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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// Enable or disable FastISel. Both options are needed, because
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// FastISel is enabled by default with -fast, and we wish to be
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// able to enable or disable fast-isel independently from -O0.
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static cl::opt<cl::boolOrDefault>
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EnableFastISelOption("fast-isel", cl::Hidden,
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cl::desc("Enable the \"fast\" instruction selector"));
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static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
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cl::desc("Show encoding in .s output"));
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static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
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cl::desc("Show instruction structure in .s output"));
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static cl::opt<cl::boolOrDefault>
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AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
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cl::init(cl::BOU_UNSET));
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static bool getVerboseAsm() {
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switch (AsmVerbose) {
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case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
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case cl::BOU_TRUE: return true;
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case cl::BOU_FALSE: return false;
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}
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llvm_unreachable("Invalid verbose asm state");
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}
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LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
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StringRef CPU, StringRef FS,
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TargetOptions Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: TargetMachine(T, Triple, CPU, FS, Options) {
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CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
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AsmInfo = T.createMCAsmInfo(Triple);
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// TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
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// and if the old one gets included then MCAsmInfo will be NULL and
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// we'll crash later.
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// Provide the user with a useful error message about what's wrong.
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assert(AsmInfo && "MCAsmInfo not initialized."
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"Make sure you include the correct TargetSelect.h"
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"and that InitializeAllTargetMCs() is being invoked!");
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}
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/// addPassesToX helper drives creation and initialization of TargetPassConfig.
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static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,
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PassManagerBase &PM,
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bool DisableVerify,
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AnalysisID StartAfter,
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AnalysisID StopAfter) {
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// Targets may override createPassConfig to provide a target-specific sublass.
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TargetPassConfig *PassConfig = TM->createPassConfig(PM);
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PassConfig->setStartStopPasses(StartAfter, StopAfter);
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// Set PassConfig options provided by TargetMachine.
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PassConfig->setDisableVerify(DisableVerify);
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PM.add(PassConfig);
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PassConfig->addIRPasses();
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PassConfig->addCodeGenPrepare();
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PassConfig->addPassesToHandleExceptions();
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PassConfig->addISelPrepare();
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// Install a MachineModuleInfo class, which is an immutable pass that holds
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// all the per-module stuff we're generating, including MCContext.
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MachineModuleInfo *MMI =
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new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(),
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&TM->getTargetLowering()->getObjFileLowering());
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PM.add(MMI);
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MCContext *Context = &MMI->getContext(); // Return the MCContext by-ref.
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// Set up a MachineFunction for the rest of CodeGen to work on.
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PM.add(new MachineFunctionAnalysis(*TM));
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// Enable FastISel with -fast, but allow that to be overridden.
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if (EnableFastISelOption == cl::BOU_TRUE ||
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(TM->getOptLevel() == CodeGenOpt::None &&
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EnableFastISelOption != cl::BOU_FALSE))
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TM->setFastISel(true);
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// Ask the target for an isel.
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if (PassConfig->addInstSelector())
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return NULL;
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PassConfig->addMachinePasses();
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PassConfig->setInitialized();
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return Context;
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}
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bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
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formatted_raw_ostream &Out,
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CodeGenFileType FileType,
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bool DisableVerify,
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AnalysisID StartAfter,
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AnalysisID StopAfter) {
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// Add common CodeGen passes.
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MCContext *Context = addPassesToGenerateCode(this, PM, DisableVerify,
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StartAfter, StopAfter);
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if (!Context)
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return true;
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if (StopAfter) {
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// FIXME: The intent is that this should eventually write out a YAML file,
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// containing the LLVM IR, the machine-level IR (when stopping after a
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// machine-level pass), and whatever other information is needed to
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// deserialize the code and resume compilation. For now, just write the
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// LLVM IR.
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PM.add(createPrintModulePass(&Out));
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return false;
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}
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if (hasMCSaveTempLabels())
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Context->setAllowTemporaryLabels(false);
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const MCAsmInfo &MAI = *getMCAsmInfo();
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const MCRegisterInfo &MRI = *getRegisterInfo();
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const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
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OwningPtr<MCStreamer> AsmStreamer;
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switch (FileType) {
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case CGFT_AssemblyFile: {
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MCInstPrinter *InstPrinter =
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getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI,
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*getInstrInfo(),
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Context->getRegisterInfo(), STI);
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// Create a code emitter if asked to show the encoding.
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MCCodeEmitter *MCE = 0;
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MCAsmBackend *MAB = 0;
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if (ShowMCEncoding) {
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const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
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MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI, STI,
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*Context);
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MAB = getTarget().createMCAsmBackend(getTargetTriple(), TargetCPU);
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}
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MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
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getVerboseAsm(),
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hasMCUseLoc(),
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hasMCUseCFI(),
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hasMCUseDwarfDirectory(),
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InstPrinter,
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MCE, MAB,
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ShowMCInst);
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AsmStreamer.reset(S);
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break;
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}
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case CGFT_ObjectFile: {
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// Create the code emitter for the target if it exists. If not, .o file
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// emission fails.
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MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI,
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STI, *Context);
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MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple(),
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TargetCPU);
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if (MCE == 0 || MAB == 0)
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return true;
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AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(),
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*Context, *MAB, Out,
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MCE, hasMCRelaxAll(),
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hasMCNoExecStack()));
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AsmStreamer.get()->InitSections();
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break;
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}
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case CGFT_Null:
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// The Null output is intended for use for performance analysis and testing,
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// not real users.
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AsmStreamer.reset(createNullStreamer(*Context));
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break;
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}
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// Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
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FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
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if (Printer == 0)
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return true;
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// If successful, createAsmPrinter took ownership of AsmStreamer.
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AsmStreamer.take();
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PM.add(Printer);
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PM.add(createGCInfoDeleter());
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return false;
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a JITCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
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JITCodeEmitter &JCE,
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bool DisableVerify) {
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// Add common CodeGen passes.
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MCContext *Context = addPassesToGenerateCode(this, PM, DisableVerify, 0, 0);
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if (!Context)
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return true;
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addCodeEmitter(PM, JCE);
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PM.add(createGCInfoDeleter());
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return false; // success!
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}
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/// addPassesToEmitMC - Add passes to the specified pass manager to get
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/// machine code emitted with the MCJIT. This method returns true if machine
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/// code is not supported. It fills the MCContext Ctx pointer which can be
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/// used to build custom MCStreamer.
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///
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bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
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MCContext *&Ctx,
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raw_ostream &Out,
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bool DisableVerify) {
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// Add common CodeGen passes.
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Ctx = addPassesToGenerateCode(this, PM, DisableVerify, 0, 0);
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if (!Ctx)
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return true;
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if (hasMCSaveTempLabels())
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Ctx->setAllowTemporaryLabels(false);
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// Create the code emitter for the target if it exists. If not, .o file
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// emission fails.
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const MCRegisterInfo &MRI = *getRegisterInfo();
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const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
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MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI,
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STI, *Ctx);
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MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple(), TargetCPU);
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if (MCE == 0 || MAB == 0)
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return true;
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OwningPtr<MCStreamer> AsmStreamer;
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AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), *Ctx,
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*MAB, Out, MCE,
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hasMCRelaxAll(),
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hasMCNoExecStack()));
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AsmStreamer.get()->InitSections();
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// Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
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FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
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if (Printer == 0)
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return true;
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// If successful, createAsmPrinter took ownership of AsmStreamer.
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AsmStreamer.take();
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PM.add(Printer);
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return false; // success!
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}
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