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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
740 lines
27 KiB
C++
740 lines
27 KiB
C++
//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <cctype>
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using namespace llvm;
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static cl::opt<bool> DisableHazardRecognizer(
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"disable-sched-hazard", cl::Hidden, cl::init(false),
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cl::desc("Disable hazard detection during preRA scheduling"));
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TargetInstrInfo::~TargetInstrInfo() {
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}
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const TargetRegisterClass*
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TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
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const TargetRegisterInfo *TRI,
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const MachineFunction &MF) const {
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if (OpNum >= MCID.getNumOperands())
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return 0;
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short RegClass = MCID.OpInfo[OpNum].RegClass;
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if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
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return TRI->getPointerRegClass(MF, RegClass);
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// Instructions like INSERT_SUBREG do not have fixed register classes.
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if (RegClass < 0)
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return 0;
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// Otherwise just look it up normally.
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return TRI->getRegClass(RegClass);
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}
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/// insertNoop - Insert a noop into the instruction stream at the specified
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/// point.
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void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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llvm_unreachable("Target didn't implement insertNoop!");
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}
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/// Measure the specified inline asm to determine an approximation of its
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/// length.
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/// Comments (which run till the next SeparatorString or newline) do not
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/// count as an instruction.
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/// Any other non-whitespace text is considered an instruction, with
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/// multiple instructions separated by SeparatorString or newlines.
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/// Variable-length instructions are not handled here; this function
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/// may be overloaded in the target code to do that.
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unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
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const MCAsmInfo &MAI) const {
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// Count the number of instructions in the asm.
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bool atInsnStart = true;
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unsigned Length = 0;
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for (; *Str; ++Str) {
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if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
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strlen(MAI.getSeparatorString())) == 0)
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atInsnStart = true;
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if (atInsnStart && !std::isspace(*Str)) {
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Length += MAI.getMaxInstLength();
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atInsnStart = false;
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}
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if (atInsnStart && strncmp(Str, MAI.getCommentString(),
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strlen(MAI.getCommentString())) == 0)
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atInsnStart = false;
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}
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return Length;
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}
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/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
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/// after it, replacing it with an unconditional branch to NewDest.
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void
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TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
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MachineBasicBlock *NewDest) const {
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MachineBasicBlock *MBB = Tail->getParent();
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// Remove all the old successors of MBB from the CFG.
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while (!MBB->succ_empty())
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MBB->removeSuccessor(MBB->succ_begin());
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// Remove all the dead instructions from the end of MBB.
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MBB->erase(Tail, MBB->end());
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// If MBB isn't immediately before MBB, insert a branch to it.
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if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
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InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
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Tail->getDebugLoc());
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MBB->addSuccessor(NewDest);
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}
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// commuteInstruction - The default implementation of this method just exchanges
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// the two operands returned by findCommutedOpIndices.
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MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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const MCInstrDesc &MCID = MI->getDesc();
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bool HasDef = MCID.getNumDefs();
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if (HasDef && !MI->getOperand(0).isReg())
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// No idea how to commute this instruction. Target should implement its own.
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return 0;
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unsigned Idx1, Idx2;
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if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
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std::string msg;
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raw_string_ostream Msg(msg);
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Msg << "Don't know how to commute: " << *MI;
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report_fatal_error(Msg.str());
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}
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assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
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"This only knows how to commute register operands so far");
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unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
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unsigned Reg1 = MI->getOperand(Idx1).getReg();
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unsigned Reg2 = MI->getOperand(Idx2).getReg();
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unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
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unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
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unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
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bool Reg1IsKill = MI->getOperand(Idx1).isKill();
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bool Reg2IsKill = MI->getOperand(Idx2).isKill();
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// If destination is tied to either of the commuted source register, then
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// it must be updated.
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if (HasDef && Reg0 == Reg1 &&
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MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
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Reg2IsKill = false;
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Reg0 = Reg2;
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SubReg0 = SubReg2;
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} else if (HasDef && Reg0 == Reg2 &&
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MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
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Reg1IsKill = false;
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Reg0 = Reg1;
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SubReg0 = SubReg1;
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}
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if (NewMI) {
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// Create a new instruction.
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MachineFunction &MF = *MI->getParent()->getParent();
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MI = MF.CloneMachineInstr(MI);
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}
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if (HasDef) {
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MI->getOperand(0).setReg(Reg0);
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MI->getOperand(0).setSubReg(SubReg0);
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}
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MI->getOperand(Idx2).setReg(Reg1);
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MI->getOperand(Idx1).setReg(Reg2);
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MI->getOperand(Idx2).setSubReg(SubReg1);
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MI->getOperand(Idx1).setSubReg(SubReg2);
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MI->getOperand(Idx2).setIsKill(Reg1IsKill);
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MI->getOperand(Idx1).setIsKill(Reg2IsKill);
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return MI;
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}
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/// findCommutedOpIndices - If specified MI is commutable, return the two
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/// operand indices that would swap value. Return true if the instruction
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/// is not in a form which this routine understands.
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bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
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unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const {
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assert(!MI->isBundle() &&
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"TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
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const MCInstrDesc &MCID = MI->getDesc();
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if (!MCID.isCommutable())
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return false;
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// This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
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// is not true, then the target must implement this.
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SrcOpIdx1 = MCID.getNumDefs();
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SrcOpIdx2 = SrcOpIdx1 + 1;
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if (!MI->getOperand(SrcOpIdx1).isReg() ||
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!MI->getOperand(SrcOpIdx2).isReg())
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// No idea.
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return false;
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return true;
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}
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bool
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TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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if (!MI->isTerminator()) return false;
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// Conditional branch is a special case.
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if (MI->isBranch() && !MI->isBarrier())
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return true;
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if (!MI->isPredicable())
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return true;
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return !isPredicated(MI);
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}
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bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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bool MadeChange = false;
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assert(!MI->isBundle() &&
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"TargetInstrInfo::PredicateInstruction() can't handle bundles");
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const MCInstrDesc &MCID = MI->getDesc();
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if (!MI->isPredicable())
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return false;
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for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (MCID.OpInfo[i].isPredicate()) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg()) {
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MO.setReg(Pred[j].getReg());
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MadeChange = true;
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} else if (MO.isImm()) {
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MO.setImm(Pred[j].getImm());
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MadeChange = true;
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} else if (MO.isMBB()) {
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MO.setMBB(Pred[j].getMBB());
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MadeChange = true;
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}
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++j;
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}
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}
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return MadeChange;
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}
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bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
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oe = MI->memoperands_end();
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o != oe;
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++o) {
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if ((*o)->isLoad() && (*o)->getValue())
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if (const FixedStackPseudoSourceValue *Value =
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dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
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FrameIndex = Value->getFrameIndex();
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MMO = *o;
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return true;
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}
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}
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return false;
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}
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bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
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oe = MI->memoperands_end();
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o != oe;
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++o) {
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if ((*o)->isStore() && (*o)->getValue())
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if (const FixedStackPseudoSourceValue *Value =
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dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
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FrameIndex = Value->getFrameIndex();
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MMO = *o;
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return true;
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}
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}
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return false;
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}
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void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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unsigned SubIdx,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const {
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MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
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MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
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MBB.insert(I, MI);
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}
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bool
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TargetInstrInfo::produceSameValue(const MachineInstr *MI0,
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const MachineInstr *MI1,
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const MachineRegisterInfo *MRI) const {
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return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
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}
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MachineInstr *TargetInstrInfo::duplicate(MachineInstr *Orig,
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MachineFunction &MF) const {
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assert(!Orig->isNotDuplicable() &&
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"Instruction cannot be duplicated");
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return MF.CloneMachineInstr(Orig);
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}
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// If the COPY instruction in MI can be folded to a stack operation, return
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// the register class to use.
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static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
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unsigned FoldIdx) {
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assert(MI->isCopy() && "MI must be a COPY instruction");
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if (MI->getNumOperands() != 2)
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return 0;
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assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
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const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
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const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
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if (FoldOp.getSubReg() || LiveOp.getSubReg())
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return 0;
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unsigned FoldReg = FoldOp.getReg();
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unsigned LiveReg = LiveOp.getReg();
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assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
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"Cannot fold physregs");
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const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
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if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
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return RC->contains(LiveOp.getReg()) ? RC : 0;
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if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
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return RC;
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// FIXME: Allow folding when register classes are memory compatible.
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return 0;
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}
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bool TargetInstrInfo::
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canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const {
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return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
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}
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/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
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/// slot into the specified machine instruction for the specified operand(s).
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/// If this is possible, a new instruction is returned with the specified
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/// operand folded, otherwise NULL is returned. The client is responsible for
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/// removing the old instruction and adding the new one in the instruction
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/// stream.
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MachineInstr*
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TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FI) const {
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unsigned Flags = 0;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i)
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if (MI->getOperand(Ops[i]).isDef())
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Flags |= MachineMemOperand::MOStore;
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else
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Flags |= MachineMemOperand::MOLoad;
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MachineBasicBlock *MBB = MI->getParent();
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assert(MBB && "foldMemoryOperand needs an inserted instruction");
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MachineFunction &MF = *MBB->getParent();
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// Ask the target to do the actual folding.
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if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) {
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// Add a memory operand, foldMemoryOperandImpl doesn't do that.
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assert((!(Flags & MachineMemOperand::MOStore) ||
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NewMI->mayStore()) &&
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"Folded a def to a non-store!");
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assert((!(Flags & MachineMemOperand::MOLoad) ||
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NewMI->mayLoad()) &&
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"Folded a use to a non-load!");
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const MachineFrameInfo &MFI = *MF.getFrameInfo();
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assert(MFI.getObjectOffset(FI) != -1);
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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Flags, MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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NewMI->addMemOperand(MF, MMO);
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// FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
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return MBB->insert(MI, NewMI);
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}
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// Straight COPY may fold as load/store.
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if (!MI->isCopy() || Ops.size() != 1)
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return 0;
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const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
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if (!RC)
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return 0;
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const MachineOperand &MO = MI->getOperand(1-Ops[0]);
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MachineBasicBlock::iterator Pos = MI;
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const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
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if (Flags == MachineMemOperand::MOStore)
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storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
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else
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loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
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return --Pos;
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}
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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MachineInstr*
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TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
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#ifndef NDEBUG
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for (unsigned i = 0, e = Ops.size(); i != e; ++i)
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assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
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#endif
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MachineBasicBlock &MBB = *MI->getParent();
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MachineFunction &MF = *MBB.getParent();
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// Ask the target to do the actual folding.
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MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
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if (!NewMI) return 0;
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NewMI = MBB.insert(MI, NewMI);
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// Copy the memoperands from the load to the folded instruction.
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NewMI->setMemRefs(LoadMI->memoperands_begin(),
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LoadMI->memoperands_end());
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return NewMI;
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}
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bool TargetInstrInfo::
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isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
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AliasAnalysis *AA) const {
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const MachineFunction &MF = *MI->getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetMachine &TM = MF.getTarget();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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// Remat clients assume operand 0 is the defined register.
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if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
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return false;
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unsigned DefReg = MI->getOperand(0).getReg();
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// A sub-register definition can only be rematerialized if the instruction
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// doesn't read the other parts of the register. Otherwise it is really a
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// read-modify-write operation on the full virtual register which cannot be
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// moved safely.
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if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
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MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
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return false;
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// A load from a fixed stack slot can be rematerialized. This may be
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// redundant with subsequent checks, but it's target-independent,
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// simple, and a common case.
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int FrameIdx = 0;
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if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
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MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
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return true;
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// Avoid instructions obviously unsafe for remat.
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if (MI->isNotDuplicable() || MI->mayStore() ||
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MI->hasUnmodeledSideEffects())
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return false;
|
|
|
|
// Don't remat inline asm. We have no idea how expensive it is
|
|
// even if it's side effect free.
|
|
if (MI->isInlineAsm())
|
|
return false;
|
|
|
|
// Avoid instructions which load from potentially varying memory.
|
|
if (MI->mayLoad() && !MI->isInvariantLoad(AA))
|
|
return false;
|
|
|
|
// If any of the registers accessed are non-constant, conservatively assume
|
|
// the instruction is not rematerializable.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0)
|
|
continue;
|
|
|
|
// Check for a well-behaved physical register.
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
if (MO.isUse()) {
|
|
// If the physreg has no defs anywhere, it's just an ambient register
|
|
// and we can freely move its uses. Alternatively, if it's allocatable,
|
|
// it could get allocated to something with a def during allocation.
|
|
if (!MRI.isConstantPhysReg(Reg, MF))
|
|
return false;
|
|
} else {
|
|
// A physreg def. We can't remat it.
|
|
return false;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// Only allow one virtual-register def. There may be multiple defs of the
|
|
// same virtual register, though.
|
|
if (MO.isDef() && Reg != DefReg)
|
|
return false;
|
|
|
|
// Don't allow any virtual-register uses. Rematting an instruction with
|
|
// virtual register uses would length the live ranges of the uses, which
|
|
// is not necessarily a good idea, certainly not "trivial".
|
|
if (MO.isUse())
|
|
return false;
|
|
}
|
|
|
|
// Everything checked out.
|
|
return true;
|
|
}
|
|
|
|
/// isSchedulingBoundary - Test if the given instruction should be
|
|
/// considered a scheduling boundary. This primarily includes labels
|
|
/// and terminators.
|
|
bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
|
|
const MachineBasicBlock *MBB,
|
|
const MachineFunction &MF) const {
|
|
// Terminators and labels can't be scheduled around.
|
|
if (MI->isTerminator() || MI->isLabel())
|
|
return true;
|
|
|
|
// Don't attempt to schedule around any instruction that defines
|
|
// a stack-oriented pointer, as it's unlikely to be profitable. This
|
|
// saves compile time, because it doesn't require every single
|
|
// stack slot reference to depend on the instruction that does the
|
|
// modification.
|
|
const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
|
|
const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
|
|
if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
// Provide a global flag for disabling the PreRA hazard recognizer that targets
|
|
// may choose to honor.
|
|
bool TargetInstrInfo::usePreRAHazardRecognizer() const {
|
|
return !DisableHazardRecognizer;
|
|
}
|
|
|
|
// Default implementation of CreateTargetRAHazardRecognizer.
|
|
ScheduleHazardRecognizer *TargetInstrInfo::
|
|
CreateTargetHazardRecognizer(const TargetMachine *TM,
|
|
const ScheduleDAG *DAG) const {
|
|
// Dummy hazard recognizer allows all instructions to issue.
|
|
return new ScheduleHazardRecognizer();
|
|
}
|
|
|
|
// Default implementation of CreateTargetMIHazardRecognizer.
|
|
ScheduleHazardRecognizer *TargetInstrInfo::
|
|
CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
|
|
const ScheduleDAG *DAG) const {
|
|
return (ScheduleHazardRecognizer *)
|
|
new ScoreboardHazardRecognizer(II, DAG, "misched");
|
|
}
|
|
|
|
// Default implementation of CreateTargetPostRAHazardRecognizer.
|
|
ScheduleHazardRecognizer *TargetInstrInfo::
|
|
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
|
|
const ScheduleDAG *DAG) const {
|
|
return (ScheduleHazardRecognizer *)
|
|
new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SelectionDAG latency interface.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
int
|
|
TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
|
|
SDNode *DefNode, unsigned DefIdx,
|
|
SDNode *UseNode, unsigned UseIdx) const {
|
|
if (!ItinData || ItinData->isEmpty())
|
|
return -1;
|
|
|
|
if (!DefNode->isMachineOpcode())
|
|
return -1;
|
|
|
|
unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
|
|
if (!UseNode->isMachineOpcode())
|
|
return ItinData->getOperandCycle(DefClass, DefIdx);
|
|
unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
|
|
return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
|
}
|
|
|
|
int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
|
|
SDNode *N) const {
|
|
if (!ItinData || ItinData->isEmpty())
|
|
return 1;
|
|
|
|
if (!N->isMachineOpcode())
|
|
return 1;
|
|
|
|
return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MachineInstr latency interface.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
unsigned
|
|
TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
|
|
const MachineInstr *MI) const {
|
|
if (!ItinData || ItinData->isEmpty())
|
|
return 1;
|
|
|
|
unsigned Class = MI->getDesc().getSchedClass();
|
|
int UOps = ItinData->Itineraries[Class].NumMicroOps;
|
|
if (UOps >= 0)
|
|
return UOps;
|
|
|
|
// The # of u-ops is dynamically determined. The specific target should
|
|
// override this function to return the right number.
|
|
return 1;
|
|
}
|
|
|
|
/// Return the default expected latency for a def based on it's opcode.
|
|
unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel,
|
|
const MachineInstr *DefMI) const {
|
|
if (DefMI->isTransient())
|
|
return 0;
|
|
if (DefMI->mayLoad())
|
|
return SchedModel->LoadLatency;
|
|
if (isHighLatencyDef(DefMI->getOpcode()))
|
|
return SchedModel->HighLatency;
|
|
return 1;
|
|
}
|
|
|
|
unsigned TargetInstrInfo::
|
|
getInstrLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr *MI,
|
|
unsigned *PredCost) const {
|
|
// Default to one cycle for no itinerary. However, an "empty" itinerary may
|
|
// still have a MinLatency property, which getStageLatency checks.
|
|
if (!ItinData)
|
|
return MI->mayLoad() ? 2 : 1;
|
|
|
|
return ItinData->getStageLatency(MI->getDesc().getSchedClass());
|
|
}
|
|
|
|
bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr *DefMI,
|
|
unsigned DefIdx) const {
|
|
if (!ItinData || ItinData->isEmpty())
|
|
return false;
|
|
|
|
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
|
int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
|
|
return (DefCycle != -1 && DefCycle <= 1);
|
|
}
|
|
|
|
/// Both DefMI and UseMI must be valid. By default, call directly to the
|
|
/// itinerary. This may be overriden by the target.
|
|
int TargetInstrInfo::
|
|
getOperandLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr *DefMI, unsigned DefIdx,
|
|
const MachineInstr *UseMI, unsigned UseIdx) const {
|
|
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
|
unsigned UseClass = UseMI->getDesc().getSchedClass();
|
|
return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
|
}
|
|
|
|
/// If we can determine the operand latency from the def only, without itinerary
|
|
/// lookup, do so. Otherwise return -1.
|
|
int TargetInstrInfo::computeDefOperandLatency(
|
|
const InstrItineraryData *ItinData,
|
|
const MachineInstr *DefMI, bool FindMin) const {
|
|
|
|
// Let the target hook getInstrLatency handle missing itineraries.
|
|
if (!ItinData)
|
|
return getInstrLatency(ItinData, DefMI);
|
|
|
|
// Return a latency based on the itinerary properties and defining instruction
|
|
// if possible. Some common subtargets don't require per-operand latency,
|
|
// especially for minimum latencies.
|
|
if (FindMin) {
|
|
// If MinLatency is valid, call getInstrLatency. This uses Stage latency if
|
|
// it exists before defaulting to MinLatency.
|
|
if (ItinData->SchedModel->MinLatency >= 0)
|
|
return getInstrLatency(ItinData, DefMI);
|
|
|
|
// If MinLatency is invalid, OperandLatency is interpreted as MinLatency.
|
|
// For empty itineraries, short-cirtuit the check and default to one cycle.
|
|
if (ItinData->isEmpty())
|
|
return 1;
|
|
}
|
|
else if(ItinData->isEmpty())
|
|
return defaultDefLatency(ItinData->SchedModel, DefMI);
|
|
|
|
// ...operand lookup required
|
|
return -1;
|
|
}
|
|
|
|
/// computeOperandLatency - Compute and return the latency of the given data
|
|
/// dependent def and use when the operand indices are already known. UseMI may
|
|
/// be NULL for an unknown use.
|
|
///
|
|
/// FindMin may be set to get the minimum vs. expected latency. Minimum
|
|
/// latency is used for scheduling groups, while expected latency is for
|
|
/// instruction cost and critical path.
|
|
///
|
|
/// Depending on the subtarget's itinerary properties, this may or may not need
|
|
/// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
|
|
/// UseIdx to compute min latency.
|
|
unsigned TargetInstrInfo::
|
|
computeOperandLatency(const InstrItineraryData *ItinData,
|
|
const MachineInstr *DefMI, unsigned DefIdx,
|
|
const MachineInstr *UseMI, unsigned UseIdx,
|
|
bool FindMin) const {
|
|
|
|
int DefLatency = computeDefOperandLatency(ItinData, DefMI, FindMin);
|
|
if (DefLatency >= 0)
|
|
return DefLatency;
|
|
|
|
assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
|
|
|
|
int OperLatency = 0;
|
|
if (UseMI)
|
|
OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
|
|
else {
|
|
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
|
OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
|
|
}
|
|
if (OperLatency >= 0)
|
|
return OperLatency;
|
|
|
|
// No operand latency was found.
|
|
unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
|
|
|
|
// Expected latency is the max of the stage latency and itinerary props.
|
|
if (!FindMin)
|
|
InstrLatency = std::max(InstrLatency,
|
|
defaultDefLatency(ItinData->SchedModel, DefMI));
|
|
return InstrLatency;
|
|
}
|