mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 19:30:10 +00:00
66f0f64082
address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
3.8 KiB
C++
104 lines
3.8 KiB
C++
//===- SparcRegisterInfo.h - Sparc Register Information Impl ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Sparc implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARCREGISTERINFO_H
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#define SPARCREGISTERINFO_H
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#include "llvm/Target/MRegisterInfo.h"
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#include "SparcGenRegisterInfo.h.inc"
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namespace llvm {
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class SparcSubtarget;
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class TargetInstrInfo;
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class Type;
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struct SparcRegisterInfo : public SparcGenRegisterInfo {
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SparcSubtarget &Subtarget;
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const TargetInstrInfo &TII;
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SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
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/// Code Generation virtual methods...
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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SmallVector<MachineOperand,4> Addr,
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const TargetRegisterClass *RC,
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SmallVector<MachineInstr*, 4> &NewMIs) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVector<MachineOperand,4> Addr,
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const TargetRegisterClass *RC,
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SmallVector<MachineInstr*, 4> &NewMIs) const;
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void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, const MachineInstr *Orig) const;
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virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
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unsigned OpNum,
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
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unsigned OpNum,
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MachineInstr* LoadMI) const {
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return 0;
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}
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const TargetRegisterClass* const* getCalleeSavedRegClasses(
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const MachineFunction *MF = 0) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS = NULL) const;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(MachineFunction &MF) const;
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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};
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} // end namespace llvm
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#endif
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