Jim Grosbach 4af58f145d ARM64: [su]xtw use W regs as inputs, not X regs. ... Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206495 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-17 20:47:31 +00:00
..
adr.s	[ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types	2014-04-09 14:44:12 +00:00
advsimd.s
aliases.s	ARM64: [su]xtw use W regs as inputs, not X regs.	2014-04-17 20:47:31 +00:00
arithmetic-encoding.s	[ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.	2014-04-09 14:44:03 +00:00
arm64-fixup.s
basic-a64-instructions.s
bitfield-encoding.s	[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.	2014-04-09 14:42:49 +00:00
branch-encoding.s	[ARM64] Conditional branches must always print their condition code, even AL.	2014-04-09 14:44:39 +00:00
crypto.s
diags.s	[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.	2014-04-09 14:43:11 +00:00
directive_loh.s
elf-relocs.s	[ARM64] Rename LR to the UAL-compliant 'X30'.	2014-04-09 14:43:59 +00:00
fp-encoding.s	[ARM64] Properly support both apple and standard syntax for FMOV	2014-04-09 14:44:49 +00:00
large-relocs.s	AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed	2014-04-15 14:00:15 +00:00
lit.local.cfg
logical-encoding.s
mapping-across-sections.s
mapping-within-section.s
memory.s	ARM64: [su]xtw use W regs as inputs, not X regs.	2014-04-17 20:47:31 +00:00
nv-cond.s	[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)	2014-04-09 14:42:07 +00:00
optional-hash.s	Optional hash symbol feature support for ARM64	2014-04-15 11:43:09 +00:00
separator.s	Fix some doc and comment typos	2014-04-09 14:47:27 +00:00
simd-ldst.s	[ARM64] Rename FP to the UAL-compliant 'X29'.	2014-04-09 14:43:50 +00:00
small-data-fixups.s
spsel-sysreg.s	[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.	2014-04-09 14:43:06 +00:00
system-encoding.s	[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.	2014-04-09 14:42:36 +00:00
tls-modifiers-darwin.s	[ARM64] Rename LR to the UAL-compliant 'X30'.	2014-04-09 14:43:59 +00:00
tls-relocs.s	[ARM64] Rename LR to the UAL-compliant 'X30'.	2014-04-09 14:43:59 +00:00
variable-exprs.s
vector-lists.s	[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}	2014-04-09 14:41:58 +00:00
verbose-vector-case.s	[ARM64] Add missing 1Q -> 1q vector kind alias	2014-04-09 14:42:01 +00:00