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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30663 91177308-0d34-0410-b5e6-96231b3b80d8
424 lines
18 KiB
C++
424 lines
18 KiB
C++
//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86ISELLOWERING_H
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#define X86ISELLOWERING_H
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#include "X86Subtarget.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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namespace llvm {
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namespace X86ISD {
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// X86 Specific DAG Nodes
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enum NodeType {
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// Start the numbering where the builtin ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
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/// SHLD, SHRD - Double shift instructions. These correspond to
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/// X86::SHLDxx and X86::SHRDxx instructions.
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SHLD,
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SHRD,
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/// FAND - Bitwise logical AND of floating point values. This corresponds
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/// to X86::ANDPS or X86::ANDPD.
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FAND,
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/// FXOR - Bitwise logical XOR of floating point values. This corresponds
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/// to X86::XORPS or X86::XORPD.
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FXOR,
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/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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/// and source type) and two outputs (FP value and token chain). FILD_FLAG
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/// also produces a flag).
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FILD,
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FILD_FLAG,
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/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
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/// integer destination in memory and a FP reg source. This corresponds
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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/// has two inputs (token chain and address) and two outputs (int value and
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/// token chain).
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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/// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
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/// which copies from ST(0) to the destination. It takes a chain and writes
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/// a RFP result and a chain.
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FP_GET_RESULT,
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/// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
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/// which copies the source operand to ST(0). It takes a chain and writes
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/// a chain and a flag.
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FP_SET_RESULT,
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/// CALL/TAILCALL - These operations represent an abstract X86 call
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/// instruction, which includes a bunch of information. In particular the
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/// operands of these node are:
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///
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/// #0 - The incoming token chain
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/// #1 - The callee
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/// #2 - The number of arg bytes the caller pushes on the stack.
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/// #3 - The number of arg bytes the callee pops off the stack.
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/// #4 - The value to pass in AL/AX/EAX (optional)
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/// #5 - The value to pass in DL/DX/EDX (optional)
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///
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/// The result values of these nodes are:
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///
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/// #0 - The outgoing token chain
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/// #1 - The first register result value (optional)
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/// #2 - The second register result value (optional)
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///
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/// The CALL vs TAILCALL distinction boils down to whether the callee is
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/// known not to modify the caller's stack frame, as is standard with
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/// LLVM.
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CALL,
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TAILCALL,
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/// RDTSC_DAG - This operation implements the lowering for
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/// readcyclecounter
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RDTSC_DAG,
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/// X86 compare and logical compare instructions.
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CMP, TEST, COMI, UCOMI,
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/// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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/// X86 conditional moves. Operand 1 and operand 2 are the two values
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/// to select from (operand 1 is a R/W operand). Operand 3 is the condition
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/// code, and operand 4 is the flag operand produced by a CMP or TEST
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/// instruction. It also writes a flag result.
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CMOV,
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/// X86 conditional branches. Operand 1 is the chain operand, operand 2
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/// is the block to branch if condition is true, operand 3 is the
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/// condition code, and operand 4 is the flag operand produced by a CMP
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/// or TEST instruction.
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BRCOND,
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/// Return with a flag operand. Operand 1 is the chain operand, operand
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/// 2 is the number of bytes of stack to pop.
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RET_FLAG,
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/// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
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REP_STOS,
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/// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
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REP_MOVS,
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/// LOAD_PACK Load a 128-bit packed float / double value. It has the same
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/// operands as a normal load.
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LOAD_PACK,
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/// LOAD_UA Load an unaligned 128-bit value. It has the same operands as
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/// a normal load.
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LOAD_UA,
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/// GlobalBaseReg - On Darwin, this node represents the result of the popl
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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/// Wrapper - A wrapper node for TargetConstantPool,
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/// TargetExternalSymbol, and TargetGlobalAddress.
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Wrapper,
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/// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
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/// have to match the operand type.
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S2VEC,
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/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRW.
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PEXTRW,
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/// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRW.
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PINSRW
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};
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// X86 specific condition code. These correspond to X86_*_COND in
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// X86InstrInfo.td. They must be kept in synch.
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enum CondCode {
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COND_A = 0,
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COND_AE = 1,
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COND_B = 2,
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COND_BE = 3,
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COND_E = 4,
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COND_G = 5,
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COND_GE = 6,
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COND_L = 7,
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COND_LE = 8,
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COND_NE = 9,
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COND_NO = 10,
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COND_NP = 11,
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COND_NS = 12,
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COND_O = 13,
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COND_P = 14,
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COND_S = 15,
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COND_INVALID
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};
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}
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/// Define some predicates that are used for node matching.
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namespace X86 {
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/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFDMask(SDNode *N);
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/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFHWMask(SDNode *N);
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/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool isPSHUFLWMask(SDNode *N);
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/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to SHUFP*.
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bool isSHUFPMask(SDNode *N);
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/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
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bool isMOVHLPSMask(SDNode *N);
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/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
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bool isMOVLPMask(SDNode *N);
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/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
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/// as well as MOVLHPS.
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bool isMOVHPMask(SDNode *N);
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/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKL.
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bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
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/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKH.
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bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
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/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
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/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
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/// <0, 0, 1, 1>
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bool isUNPCKL_v_undef_Mask(SDNode *N);
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/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSS,
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/// MOVSD, and MOVD, i.e. setting the lowest element.
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bool isMOVLMask(SDNode *N);
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/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
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bool isMOVSHDUPMask(SDNode *N);
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/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
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bool isMOVSLDUPMask(SDNode *N);
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element.
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bool isSplatMask(SDNode *N);
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/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
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/// instructions.
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unsigned getShuffleSHUFImmediate(SDNode *N);
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/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
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/// instructions.
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unsigned getShufflePSHUFHWImmediate(SDNode *N);
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/// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
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/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
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/// instructions.
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unsigned getShufflePSHUFLWImmediate(SDNode *N);
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}
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//===----------------------------------------------------------------------===//
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// X86TargetLowering - X86 Implementation of the TargetLowering interface
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class X86TargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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int RegSaveFrameIndex; // X86-64 vararg func register save area.
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unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
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unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
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int ReturnAddrIndex; // FrameIndex for return slot.
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int BytesToPopOnReturn; // Number of arg bytes ret should pop.
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int BytesCallerReserves; // Number of arg bytes caller makes.
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public:
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X86TargetLowering(TargetMachine &TM);
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// Return the number of bytes that a function should pop when it returns (in
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// addition to the space used by the return address).
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//
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unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
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// Return the number of bytes that the caller reserves for arguments passed
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// to this function.
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unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified
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/// in Mask are known to be either zero or one and return them in the
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/// KnownZero/KnownOne bitsets.
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virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
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uint64_t Mask,
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uint64_t &KnownZero,
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uint64_t &KnownOne,
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unsigned Depth = 0) const;
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SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
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ConstraintType getConstraintType(char ConstraintLetter) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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/// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
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/// {edx}), return the register number and the register class for the
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/// register. This should only be used for C_Register constraints. On error,
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/// this returns a register number of 0.
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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/// isLegalAddressImmediate - Return true if the integer value or
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/// GlobalValue can be used as the offset of the target addressing mode.
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virtual bool isLegalAddressImmediate(int64_t V) const;
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virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
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/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
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/// used by Targets can use this to indicate if there is a suitable
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/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
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/// pool entry.
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virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
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MVT::ValueType EVT,
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SelectionDAG &DAG) const;
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private:
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
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/// X86StackPtr - X86 physical register used as stack ptr.
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unsigned X86StackPtr;
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/// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
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bool X86ScalarSSE;
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// C Calling Convention implementation.
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SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG);
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// X86-64 C Calling Convention implementation.
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SDOperand LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG);
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// Fast Calling Convention implementation.
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SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
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bool isFastCall);
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// StdCall Calling Convention implementation.
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SDOperand LowerStdCallCCArguments(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerStdCallCCCallTo(SDOperand Op, SelectionDAG &DAG);
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// FastCall Calling Convention implementation.
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SDOperand LowerFastCallCCArguments(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG, SDOperand Chain);
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SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
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};
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}
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// FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
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// to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
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// EDX". Anything more is illegal.
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//
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// FIXME: The linscan register allocator currently has problem with
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// coalescing. At the time of this writing, whenever it decides to coalesce
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// a physreg with a virtreg, this increases the size of the physreg's live
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// range, and the live range cannot ever be reduced. This causes problems if
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// too many physregs are coaleced with virtregs, which can cause the register
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// allocator to wedge itself.
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//
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// This code triggers this problem more often if we pass args in registers,
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// so disable it until this is fixed.
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//
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#define FASTCC_NUM_INT_ARGS_INREGS 0
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#endif // X86ISELLOWERING_H
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