mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-06 09:54:49 +00:00
f49810c7e6
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng. I've done my best to consolidate the patches with those that were done by Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed anything. I've completely reorganized the thumb2 td file, made more extensive uses of multiclass, etc. Test cases will be contributed later after I re-organize what's in svn first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73965 91177308-0d34-0410-b5e6-96231b3b80d8
441 lines
16 KiB
TableGen
441 lines
16 KiB
TableGen
//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Thumb2 instruction set.
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//
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//===----------------------------------------------------------------------===//
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// Shifted operands. No register controlled shifts for Thumb2.
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// Note: We do not support rrx shifted operands yet.
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def t2_so_reg : Operand<i32>, // reg imm
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ComplexPattern<i32, 2, "SelectShifterOperand",
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[shl,srl,sra,rotr]> {
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let PrintMethod = "printSOOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
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// described for t2_so_imm def below.
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def t2_so_imm_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
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}]>;
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// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
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def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
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}]>;
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// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
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def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
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}]>;
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// t2_so_imm - Match a 32-bit immediate operand, which is an
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// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
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// immediate splatted into multiple bytes of the word. t2_so_imm values are
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// represented in the imm field in the same 12-bit form that they are encoded
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// into t2_so_imm instructions: the 8-bit immediate is the least significant bits
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// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
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def t2_so_imm : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
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}], t2_so_imm_XFORM> {
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let PrintMethod = "printT2SOImmOperand";
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}
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// t2_so_imm_not - Match an immediate that is a complement
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// of a t2_so_imm.
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def t2_so_imm_not : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
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}], t2_so_imm_not_XFORM> {
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let PrintMethod = "printT2SOImmOperand";
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}
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// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
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def t2_so_imm_neg : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
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}], t2_so_imm_neg_XFORM> {
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let PrintMethod = "printT2SOImmOperand";
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}
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/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
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def imm0_4095 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 4096;
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}]>;
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def imm0_4095_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)(-N->getZExtValue()) < 4096;
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}], imm_neg_XFORM>;
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/// imm0_65535 predicate - True if the 32-bit immediate is in the range
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/// [0.65535].
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def imm0_65535 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 65536;
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}]>;
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/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
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/// e.g., 0xf000ffff
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def bf_inv_mask_imm : Operand<i32>,
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PatLeaf<(imm), [{
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uint32_t v = (uint32_t)N->getZExtValue();
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if (v == 0xffffffff)
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return 0;
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// naive checker. should do better, but simple is best for now since it's
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// more likely to be correct.
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while (v & 1) v >>= 1; // shift off the leading 1's
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if (v)
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{
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while (!(v & 1)) v >>=1; // shift off the mask
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while (v & 1) v >>= 1; // shift off the trailing 1's
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}
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// if this is a mask for clearing a bitfield, what's left should be zero.
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return (v == 0);
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}] > {
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let PrintMethod = "printBitfieldInvMaskImmOperand";
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}
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/// Split a 32-bit immediate into two 16 bit parts.
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def t2_lo16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
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MVT::i32);
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}]>;
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def t2_hi16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
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}]>;
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def t2_lo16AllZero : PatLeaf<(i32 imm), [{
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// Returns true if all low 16-bits are 0.
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return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
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}], t2_hi16>;
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//===----------------------------------------------------------------------===//
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// Thumb2 to cover the functionality of the ARM instruction set.
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//
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/// T2I_bin_is - Defines a set of (op reg, {so_imm|so_reg}) patterns for a
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// binary operation that produces a value.
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multiclass T2I_bin_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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/// T2I_2bin_is - Same as T2I_bin_is except the order of operands are reversed.
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multiclass T2I_rbin_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
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}
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/// T2I_bin_s_is - Similar to T2I_bin_is except it sets the 's' bit so the
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/// instruction modifies the CPSR register.
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let Defs = [CPSR] in {
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multiclass T2I_bin_s_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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}
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/// T2I_rbin_s_is - Same as T2I_bin_s_is except the order of operands are
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/// reversed.
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let Defs = [CPSR] in {
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multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
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}
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}
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/// T2I_bin_ii12s - Defines a set of (op reg, {so_imm|imm0_4095|so_reg}) patterns
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/// for a binary operation that produces a value.
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multiclass T2I_bin_ii12s<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// 12-bit imm
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def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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!strconcat(opc, "w $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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/// T2I_bin_c_is - Defines a set of (op reg, {so_imm|reg}) patterns for a
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// binary operation that produces a value and set the carry bit. It can also
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/// optionally set CPSR.
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let Uses = [CPSR] in {
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multiclass T2I_bin_c_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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}
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/// T2I_rbin_c_is - Same as T2I_bin_c_is except the order of operands are
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/// reversed.
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let Uses = [CPSR] in {
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multiclass T2I_rbin_c_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
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}
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}
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/// T21_cmp_irs - Defines a set of (op r, {so_imm|so_reg}) cmp / test
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/// patterns. Similar to T2I_bin_is except the instruction does not produce
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/// a explicit result, only implicitly set CPSR.
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let Uses = [CPSR] in {
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multiclass T2I_cmp_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, " $lhs, $rhs"),
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[(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
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// shifted register
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def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, " $lhs, $rhs"),
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[(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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//===----------------------------------------------------------------------===//
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// Move Instructions.
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//
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let neverHasSideEffects = 1 in
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def t2MOVr : T2I<(outs GPR:$dst), (ins GPR:$src),
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"mov $dst, $src", []>;
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def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
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"movw $dst, $src",
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[(set GPR:$dst, imm0_65535:$src)]>;
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// FIXME: Move (shifted register) is a pseudo-instruction for ASR, LSL, LSR,
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// ROR, and RRX. Consider splitting into multiple instructions.
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def t2MOVs : T2I<(outs GPR:$dst), (ins so_reg:$src),
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"mov $dst, $src",
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[(set GPR:$dst, so_reg:$src)]>;
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def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src),
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"mov $dst, $src, rrx",
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[(set GPR:$dst, (ARMrrx GPR:$src))]>;
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// FIXME: Also available in ARM mode.
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let Constraints = "$src = $dst" in
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def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
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"movt $dst, $imm",
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[(set GPR:$dst,
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(or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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defm t2ADD : T2I_bin_ii12s<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
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defm t2SUB : T2I_bin_ii12s<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
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defm t2ADDS : T2I_bin_s_is<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
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defm t2SUBS : T2I_bin_s_is<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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// FIXME: predication support
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defm t2ADC : T2I_bin_c_is<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm t2SBC : T2I_bin_c_is<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// RSB, RSC
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defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
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defm t2RSBS : T2I_rbin_c_is<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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defm t2RSC : T2I_rbin_s_is<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
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(t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
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def : Thumb2Pat<(add GPR:$src, imm0_4095_neg:$imm),
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(t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
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//===----------------------------------------------------------------------===//
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// Bitwise Instructions.
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//
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defm t2AND : T2I_bin_is <"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
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defm t2ORR : T2I_bin_is <"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
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defm t2EOR : T2I_bin_is <"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
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defm t2BIC : T2I_bin_is <"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
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def : Thumb2Pat<(and GPR:$src, t2_so_imm_not:$imm),
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(t2BICri GPR:$src, t2_so_imm_not:$imm)>;
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defm t2ORN : T2I_bin_is <"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
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def : Thumb2Pat<(or GPR:$src, t2_so_imm_not:$imm),
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(t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
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def t2MVNr : T2I<(outs GPR:$dst), (ins t2_so_reg:$rhs),
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"mvn $dst, $rhs",
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[(set GPR:$dst, (not t2_so_reg:$rhs))]>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def t2MVNi : T2I<(outs GPR:$dst), (ins t2_so_imm_not:$rhs),
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"mvn $dst, $rhs",
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[(set GPR:$dst, t2_so_imm_not:$rhs)]>;
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// A8.6.17 BFC - Bitfield clear
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// FIXME: Also available in ARM mode.
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let Constraints = "$src = $dst" in
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def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
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"bfc $dst, $imm",
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[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
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// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
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//===----------------------------------------------------------------------===//
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// Multiply Instructions.
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//
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def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
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"mul $dst, $a, $b",
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[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
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def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
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"mla $dst, $a, $b, $c",
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[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
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def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
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"mls $dst, $a, $b, $c",
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[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
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// FIXME: SMULL, etc.
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//===----------------------------------------------------------------------===//
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// Misc. Arithmetic Instructions.
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//
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/////
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/// A8.6.31 CLZ
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/////
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// FIXME not firing? but ARM version does...
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def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
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"clz $dst, $src",
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[(set GPR:$dst, (ctlz GPR:$src))]>;
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def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
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"rev $dst, $src",
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[(set GPR:$dst, (bswap GPR:$src))]>;
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def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
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"rev16 $dst, $src",
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[(set GPR:$dst,
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(or (and (srl GPR:$src, (i32 8)), 0xFF),
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(or (and (shl GPR:$src, (i32 8)), 0xFF00),
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(or (and (srl GPR:$src, (i32 8)), 0xFF0000),
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(and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
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/////
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/// A8.6.137 REVSH
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/////
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def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
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"revsh $dst, $src",
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[(set GPR:$dst,
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(sext_inreg
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(or (srl (and GPR:$src, 0xFFFF), (i32 8)),
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(shl GPR:$src, (i32 8))), i16))]>;
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// FIXME: PKHxx etc.
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//===----------------------------------------------------------------------===//
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// Comparison Instructions...
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//
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defm t2CMP : T2I_cmp_is<"cmp",
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BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
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defm t2CMPnz : T2I_cmp_is<"cmp",
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BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
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defm t2CMN : T2I_cmp_is<"cmn",
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BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
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defm t2CMNnz : T2I_cmp_is<"cmn",
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BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
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def : Thumb2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
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(t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
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def : Thumb2Pat<(ARMcmpNZ GPR:$src, t2_so_imm_neg:$imm),
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(t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
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// FIXME: TST, TEQ, etc.
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// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
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// Short range conditional branch. Looks awesome for loops. Need to figure
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// out how to use this one.
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// FIXME: Conditional moves
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//
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// Large immediate handling.
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def : Thumb2Pat<(i32 imm:$src),
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(t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)),
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(t2_hi16 imm:$src))>;
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