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https://github.com/c64scene-ar/llvm-6502.git
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cd828618b8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
237 lines
9.0 KiB
C++
237 lines
9.0 KiB
C++
//===- ARMRegisterInfo.td - ARM Register defs -------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the ARM register file
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//===----------------------------------------------------------------------===//
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// Registers are identified with 4-bit ID numbers.
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class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
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field bits<4> Num;
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let Namespace = "ARM";
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let SubRegs = subregs;
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}
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class ARMFReg<bits<5> num, string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "ARM";
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}
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// Integer registers
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def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
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def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
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def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
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def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
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def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
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def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
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def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
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def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
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def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
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def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
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def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
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def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
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def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
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def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
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def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
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def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
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// Float registers
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def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
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def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;
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def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;
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def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;
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def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;
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def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
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def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
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def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
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def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
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def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
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def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
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def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
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def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
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def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
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def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
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def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
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// Aliases of the F* registers used to hold 64-bit fp values (doubles)
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def D0 : ARMReg< 0, "d0", [S0, S1]>;
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def D1 : ARMReg< 1, "d1", [S2, S3]>;
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def D2 : ARMReg< 2, "d2", [S4, S5]>;
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def D3 : ARMReg< 3, "d3", [S6, S7]>;
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def D4 : ARMReg< 4, "d4", [S8, S9]>;
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def D5 : ARMReg< 5, "d5", [S10, S11]>;
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def D6 : ARMReg< 6, "d6", [S12, S13]>;
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def D7 : ARMReg< 7, "d7", [S14, S15]>;
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def D8 : ARMReg< 8, "d8", [S16, S17]>;
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def D9 : ARMReg< 9, "d9", [S18, S19]>;
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def D10 : ARMReg<10, "d10", [S20, S21]>;
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def D11 : ARMReg<11, "d11", [S22, S23]>;
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def D12 : ARMReg<12, "d12", [S24, S25]>;
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def D13 : ARMReg<13, "d13", [S26, S27]>;
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def D14 : ARMReg<14, "d14", [S28, S29]>;
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def D15 : ARMReg<15, "d15", [S30, S31]>;
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// Current Program Status Register.
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def CPSR : ARMReg<0, "cpsr">;
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// Register classes.
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//
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// pc == Program Counter
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// lr == Link Register
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// sp == Stack Pointer
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// r12 == ip (scratch)
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// r7 == Frame Pointer (thumb-style backtraces)
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// r11 == Frame Pointer (arm-style backtraces)
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// r10 == Stack Limit
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//
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def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
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R7, R8, R9, R10, R12, R11,
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LR, SP, PC]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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// FIXME: We are reserving r12 in case the PEI needs to use it to
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// generate large stack offset. Make it available once we have register
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// scavenging. Similarly r3 is reserved in Thumb mode for now.
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let MethodBodies = [{
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// FP is R11, R9 is available.
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static const unsigned ARM_GPR_AO_1[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R9, ARM::R10,
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ARM::R11 };
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// FP is R11, R9 is not available.
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static const unsigned ARM_GPR_AO_2[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R10,
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ARM::R11 };
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// FP is R7, R9 is available.
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static const unsigned ARM_GPR_AO_3[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6,
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ARM::R8, ARM::R9, ARM::R10,ARM::R11,
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ARM::R7 };
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// FP is R7, R9 is not available.
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static const unsigned ARM_GPR_AO_4[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6,
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ARM::R8, ARM::R10,ARM::R11,
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ARM::R7 };
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GPRClass::iterator
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GPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isTargetDarwin()) {
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if (Subtarget.isR9Reserved())
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return ARM_GPR_AO_4;
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else
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return ARM_GPR_AO_3;
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} else {
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if (Subtarget.isR9Reserved())
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return ARM_GPR_AO_2;
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else
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return ARM_GPR_AO_1;
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}
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}
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GPRClass::iterator
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GPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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GPRClass::iterator I;
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if (Subtarget.isTargetDarwin()) {
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if (Subtarget.isR9Reserved()) {
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I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
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} else {
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I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
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}
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} else {
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if (Subtarget.isR9Reserved()) {
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I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
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} else {
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I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
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}
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}
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// Mac OS X requires FP not to be clobbered for backtracing purpose.
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return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
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}
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}];
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}
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// Thumb registers are R0-R7 normally. Some instructions can still use
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// the general GPR register class above (MOV, e.g.)
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def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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// FIXME: We are reserving r3 in Thumb mode in case the PEI needs to use it
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// to generate large stack offset. Make it available once we have register
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// scavenging.
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let MethodBodies = [{
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static const unsigned THUMB_tGPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
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// FP is R7, only low registers available.
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tGPRClass::iterator
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tGPRClass::allocation_order_begin(const MachineFunction &MF) const {
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return THUMB_tGPR_AO;
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}
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tGPRClass::iterator
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tGPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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tGPRClass::iterator I =
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THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned));
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// Mac OS X requires FP not to be clobbered for backtracing purpose.
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return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
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}
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}];
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}
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def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
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S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
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S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
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// ARM requires only word alignment for double. It's more performant if it
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// is double-word alignment though.
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def DPR : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, D8,
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D9, D10, D11, D12, D13, D14, D15]>;
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// Condition code registers.
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def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
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//===----------------------------------------------------------------------===//
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// Subregister Set Definitions... now that we have all of the pieces, define the
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// sub registers for each register.
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//
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def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15],
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[S0, S2, S4, S6, S8, S10, S12, S14,
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S16, S18, S20, S22, S24, S26, S28, S30]>;
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def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15],
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[S1, S3, S5, S7, S9, S11, S13, S15,
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S17, S19, S21, S23, S25, S27, S29, S31]>;
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