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https://github.com/c64scene-ar/llvm-6502.git
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f4ccd11075
This compiles with no changes to clang/lld/lldb with MSVC and includes overloads to various functions which are used by those projects and llvm which have OwningPtr's as parameters. This should allow out of tree projects some time to move. There are also no changes to libs/Target, which should help out of tree targets have time to move, if necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203083 91177308-0d34-0410-b5e6-96231b3b80d8
363 lines
13 KiB
C++
363 lines
13 KiB
C++
//===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Disassembler.h"
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#include "llvm-c/Disassembler.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCRelocationInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbolizer.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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namespace llvm {
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class Target;
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} // namespace llvm
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using namespace llvm;
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// LLVMCreateDisasm() creates a disassembler for the TripleName. Symbolic
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// disassembly is supported by passing a block of information in the DisInfo
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// parameter and specifying the TagType and callback functions as described in
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// the header llvm-c/Disassembler.h . The pointer to the block and the
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// functions can all be passed as NULL. If successful, this returns a
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// disassembler context. If not, it returns NULL.
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//
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LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *Triple, const char *CPU,
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void *DisInfo, int TagType,
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LLVMOpInfoCallback GetOpInfo,
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LLVMSymbolLookupCallback SymbolLookUp){
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// Get the target.
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std::string Error;
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const Target *TheTarget = TargetRegistry::lookupTarget(Triple, Error);
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if (!TheTarget)
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return 0;
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const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple);
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if (!MRI)
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return 0;
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// Get the assembler info needed to setup the MCContext.
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const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple);
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if (!MAI)
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return 0;
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const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
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if (!MII)
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return 0;
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// Package up features to be passed to target/subtarget
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std::string FeaturesStr;
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const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU,
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FeaturesStr);
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if (!STI)
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return 0;
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// Set up the MCContext for creating symbols and MCExpr's.
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MCContext *Ctx = new MCContext(MAI, MRI, 0);
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if (!Ctx)
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return 0;
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// Set up disassembler.
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MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI);
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if (!DisAsm)
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return 0;
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std::unique_ptr<MCRelocationInfo> RelInfo(
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TheTarget->createMCRelocationInfo(Triple, *Ctx));
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if (!RelInfo)
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return 0;
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std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
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Triple, GetOpInfo, SymbolLookUp, DisInfo, Ctx, RelInfo.release()));
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DisAsm->setSymbolizer(Symbolizer);
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DisAsm->setupForSymbolicDisassembly(GetOpInfo, SymbolLookUp, DisInfo,
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Ctx, RelInfo);
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// Set up the instruction printer.
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int AsmPrinterVariant = MAI->getAssemblerDialect();
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MCInstPrinter *IP = TheTarget->createMCInstPrinter(AsmPrinterVariant,
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*MAI, *MII, *MRI, *STI);
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if (!IP)
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return 0;
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LLVMDisasmContext *DC = new LLVMDisasmContext(Triple, DisInfo, TagType,
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GetOpInfo, SymbolLookUp,
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TheTarget, MAI, MRI,
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STI, MII, Ctx, DisAsm, IP);
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if (!DC)
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return 0;
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DC->setCPU(CPU);
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return DC;
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}
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LLVMDisasmContextRef LLVMCreateDisasm(const char *Triple, void *DisInfo,
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int TagType, LLVMOpInfoCallback GetOpInfo,
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LLVMSymbolLookupCallback SymbolLookUp) {
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return LLVMCreateDisasmCPU(Triple, "", DisInfo, TagType, GetOpInfo,
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SymbolLookUp);
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}
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//
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// LLVMDisasmDispose() disposes of the disassembler specified by the context.
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//
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void LLVMDisasmDispose(LLVMDisasmContextRef DCR){
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LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
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delete DC;
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}
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namespace {
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//
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// The memory object created by LLVMDisasmInstruction().
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//
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class DisasmMemoryObject : public MemoryObject {
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uint8_t *Bytes;
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uint64_t Size;
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uint64_t BasePC;
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public:
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DisasmMemoryObject(uint8_t *bytes, uint64_t size, uint64_t basePC) :
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Bytes(bytes), Size(size), BasePC(basePC) {}
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uint64_t getBase() const { return BasePC; }
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uint64_t getExtent() const { return Size; }
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int readByte(uint64_t Addr, uint8_t *Byte) const {
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if (Addr - BasePC >= Size)
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return -1;
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*Byte = Bytes[Addr - BasePC];
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return 0;
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}
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};
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} // end anonymous namespace
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/// \brief Emits the comments that are stored in \p DC comment stream.
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/// Each comment in the comment stream must end with a newline.
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static void emitComments(LLVMDisasmContext *DC,
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formatted_raw_ostream &FormattedOS) {
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// Flush the stream before taking its content.
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DC->CommentStream.flush();
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StringRef Comments = DC->CommentsToEmit.str();
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// Get the default information for printing a comment.
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const MCAsmInfo *MAI = DC->getAsmInfo();
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const char *CommentBegin = MAI->getCommentString();
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unsigned CommentColumn = MAI->getCommentColumn();
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bool IsFirst = true;
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while (!Comments.empty()) {
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if (!IsFirst)
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FormattedOS << '\n';
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// Emit a line of comments.
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FormattedOS.PadToColumn(CommentColumn);
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size_t Position = Comments.find('\n');
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FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position);
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// Move after the newline character.
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Comments = Comments.substr(Position+1);
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IsFirst = false;
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}
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FormattedOS.flush();
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// Tell the comment stream that the vector changed underneath it.
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DC->CommentsToEmit.clear();
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DC->CommentStream.resync();
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}
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/// \brief Gets latency information for \p Inst form the itinerary
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/// scheduling model, based on \p DC information.
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/// \return The maximum expected latency over all the operands or -1
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/// if no information are available.
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static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
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const int NoInformationAvailable = -1;
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// Check if we have a CPU to get the itinerary information.
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if (DC->getCPU().empty())
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return NoInformationAvailable;
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// Get itinerary information.
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const MCSubtargetInfo *STI = DC->getSubtargetInfo();
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InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
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// Get the scheduling class of the requested instruction.
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const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
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unsigned SCClass = Desc.getSchedClass();
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int Latency = 0;
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for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
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++OpIdx)
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Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
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return Latency;
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}
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/// \brief Gets latency information for \p Inst, based on \p DC information.
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/// \return The maximum expected latency over all the definitions or -1
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/// if no information are available.
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static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
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// Try to compute scheduling information.
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const MCSubtargetInfo *STI = DC->getSubtargetInfo();
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const MCSchedModel *SCModel = STI->getSchedModel();
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const int NoInformationAvailable = -1;
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// Check if we have a scheduling model for instructions.
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if (!SCModel || !SCModel->hasInstrSchedModel())
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// Try to fall back to the itinerary model if we do not have a
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// scheduling model.
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return getItineraryLatency(DC, Inst);
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// Get the scheduling class of the requested instruction.
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const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
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unsigned SCClass = Desc.getSchedClass();
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const MCSchedClassDesc *SCDesc = SCModel->getSchedClassDesc(SCClass);
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// Resolving the variant SchedClass requires an MI to pass to
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// SubTargetInfo::resolveSchedClass.
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if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
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return NoInformationAvailable;
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// Compute output latency.
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int Latency = 0;
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for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
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DefIdx != DefEnd; ++DefIdx) {
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// Lookup the definition's write latency in SubtargetInfo.
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const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
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DefIdx);
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Latency = std::max(Latency, WLEntry->Cycles);
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}
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return Latency;
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}
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/// \brief Emits latency information in DC->CommentStream for \p Inst, based
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/// on the information available in \p DC.
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static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
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int Latency = getLatency(DC, Inst);
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// Report only interesting latency.
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if (Latency < 2)
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return;
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DC->CommentStream << "Latency: " << Latency << '\n';
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}
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//
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// LLVMDisasmInstruction() disassembles a single instruction using the
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// disassembler context specified in the parameter DC. The bytes of the
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// instruction are specified in the parameter Bytes, and contains at least
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// BytesSize number of bytes. The instruction is at the address specified by
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// the PC parameter. If a valid instruction can be disassembled its string is
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// returned indirectly in OutString which whos size is specified in the
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// parameter OutStringSize. This function returns the number of bytes in the
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// instruction or zero if there was no valid instruction. If this function
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// returns zero the caller will have to pick how many bytes they want to step
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// over by printing a .byte, .long etc. to continue.
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//
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size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
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uint64_t BytesSize, uint64_t PC, char *OutString,
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size_t OutStringSize){
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LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
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// Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject.
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DisasmMemoryObject MemoryObject(Bytes, BytesSize, PC);
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uint64_t Size;
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MCInst Inst;
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const MCDisassembler *DisAsm = DC->getDisAsm();
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MCInstPrinter *IP = DC->getIP();
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MCDisassembler::DecodeStatus S;
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SmallVector<char, 64> InsnStr;
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raw_svector_ostream Annotations(InsnStr);
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S = DisAsm->getInstruction(Inst, Size, MemoryObject, PC,
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/*REMOVE*/ nulls(), Annotations);
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switch (S) {
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case MCDisassembler::Fail:
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case MCDisassembler::SoftFail:
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// FIXME: Do something different for soft failure modes?
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return 0;
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case MCDisassembler::Success: {
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Annotations.flush();
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StringRef AnnotationsStr = Annotations.str();
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SmallVector<char, 64> InsnStr;
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raw_svector_ostream OS(InsnStr);
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formatted_raw_ostream FormattedOS(OS);
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IP->printInst(&Inst, FormattedOS, AnnotationsStr);
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if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency)
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emitLatency(DC, Inst);
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emitComments(DC, FormattedOS);
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OS.flush();
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assert(OutStringSize != 0 && "Output buffer cannot be zero size");
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size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
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std::memcpy(OutString, InsnStr.data(), OutputSize);
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OutString[OutputSize] = '\0'; // Terminate string.
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return Size;
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}
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}
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llvm_unreachable("Invalid DecodeStatus!");
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}
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//
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// LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
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// can set all the Options and 0 otherwise.
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//
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int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
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if (Options & LLVMDisassembler_Option_UseMarkup){
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LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
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MCInstPrinter *IP = DC->getIP();
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IP->setUseMarkup(1);
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DC->addOptions(LLVMDisassembler_Option_UseMarkup);
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Options &= ~LLVMDisassembler_Option_UseMarkup;
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}
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if (Options & LLVMDisassembler_Option_PrintImmHex){
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LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
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MCInstPrinter *IP = DC->getIP();
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IP->setPrintImmHex(1);
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DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
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Options &= ~LLVMDisassembler_Option_PrintImmHex;
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}
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if (Options & LLVMDisassembler_Option_AsmPrinterVariant){
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LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
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// Try to set up the new instruction printer.
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const MCAsmInfo *MAI = DC->getAsmInfo();
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const MCInstrInfo *MII = DC->getInstrInfo();
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const MCRegisterInfo *MRI = DC->getRegisterInfo();
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const MCSubtargetInfo *STI = DC->getSubtargetInfo();
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int AsmPrinterVariant = MAI->getAssemblerDialect();
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AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
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MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
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AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
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if (IP) {
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DC->setIP(IP);
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DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
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Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
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}
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}
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if (Options & LLVMDisassembler_Option_SetInstrComments) {
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LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
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MCInstPrinter *IP = DC->getIP();
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IP->setCommentStream(DC->CommentStream);
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DC->addOptions(LLVMDisassembler_Option_SetInstrComments);
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Options &= ~LLVMDisassembler_Option_SetInstrComments;
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}
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if (Options & LLVMDisassembler_Option_PrintLatency) {
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LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
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DC->addOptions(LLVMDisassembler_Option_PrintLatency);
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Options &= ~LLVMDisassembler_Option_PrintLatency;
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}
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return (Options == 0);
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}
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