mirror of
https://github.com/c64scene-ar/llvm-6502.git
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536a88ad5b
store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164132 91177308-0d34-0410-b5e6-96231b3b80d8
475 lines
15 KiB
C++
475 lines
15 KiB
C++
//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "MCTargetDesc/X86FixupKinds.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionCOFF.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/Object/MachOFormat.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Option to allow disabling arithmetic relaxation to workaround PR9807, which
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// is useful when running bitwise comparison experiments on Darwin. We should be
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// able to remove this once PR9807 is resolved.
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static cl::opt<bool>
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MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
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cl::desc("Disable relaxation of arithmetic instruction for X86"));
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static unsigned getFixupKindLog2Size(unsigned Kind) {
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switch (Kind) {
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default: llvm_unreachable("invalid fixup kind!");
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case FK_PCRel_1:
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case FK_SecRel_1:
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case FK_Data_1: return 0;
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case FK_PCRel_2:
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case FK_SecRel_2:
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case FK_Data_2: return 1;
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case FK_PCRel_4:
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case X86::reloc_riprel_4byte:
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case X86::reloc_riprel_4byte_movq_load:
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case X86::reloc_signed_4byte:
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case X86::reloc_global_offset_table:
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case FK_SecRel_4:
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case FK_Data_4: return 2;
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case FK_PCRel_8:
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case FK_SecRel_8:
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case FK_Data_8: return 3;
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}
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}
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namespace {
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class X86ELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
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bool HasRelocationAddend, bool foobar)
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: MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
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};
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class X86AsmBackend : public MCAsmBackend {
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StringRef CPU;
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public:
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X86AsmBackend(const Target &T, StringRef _CPU)
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: MCAsmBackend(), CPU(_CPU) {}
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unsigned getNumFixupKinds() const {
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return X86::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
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{ "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
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{ "reloc_signed_4byte", 0, 4 * 8, 0},
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{ "reloc_global_offset_table", 0, 4 * 8, 0}
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const {
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unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
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assert(Fixup.getOffset() + Size <= DataSize &&
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"Invalid fixup offset!");
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// Check that uppper bits are either all zeros or all ones.
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// Specifically ignore overflow/underflow as long as the leakage is
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// limited to the lower bits. This is to remain compatible with
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// other assemblers.
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assert(isIntN(Size * 8 + 1, Value) &&
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"Value does not fit in the Fixup field");
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for (unsigned i = 0; i != Size; ++i)
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Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
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}
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bool mayNeedRelaxation(const MCInst &Inst) const;
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCInstFragment *DF,
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const MCAsmLayout &Layout) const;
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
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};
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} // end anonymous namespace
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static unsigned getRelaxedOpcodeBranch(unsigned Op) {
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switch (Op) {
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default:
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return Op;
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case X86::JAE_1: return X86::JAE_4;
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case X86::JA_1: return X86::JA_4;
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case X86::JBE_1: return X86::JBE_4;
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case X86::JB_1: return X86::JB_4;
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case X86::JE_1: return X86::JE_4;
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case X86::JGE_1: return X86::JGE_4;
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case X86::JG_1: return X86::JG_4;
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case X86::JLE_1: return X86::JLE_4;
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case X86::JL_1: return X86::JL_4;
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case X86::JMP_1: return X86::JMP_4;
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case X86::JNE_1: return X86::JNE_4;
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case X86::JNO_1: return X86::JNO_4;
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case X86::JNP_1: return X86::JNP_4;
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case X86::JNS_1: return X86::JNS_4;
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case X86::JO_1: return X86::JO_4;
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case X86::JP_1: return X86::JP_4;
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case X86::JS_1: return X86::JS_4;
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}
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}
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static unsigned getRelaxedOpcodeArith(unsigned Op) {
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switch (Op) {
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default:
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return Op;
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// IMUL
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case X86::IMUL16rri8: return X86::IMUL16rri;
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case X86::IMUL16rmi8: return X86::IMUL16rmi;
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case X86::IMUL32rri8: return X86::IMUL32rri;
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case X86::IMUL32rmi8: return X86::IMUL32rmi;
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case X86::IMUL64rri8: return X86::IMUL64rri32;
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case X86::IMUL64rmi8: return X86::IMUL64rmi32;
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// AND
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case X86::AND16ri8: return X86::AND16ri;
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case X86::AND16mi8: return X86::AND16mi;
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case X86::AND32ri8: return X86::AND32ri;
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case X86::AND32mi8: return X86::AND32mi;
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case X86::AND64ri8: return X86::AND64ri32;
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case X86::AND64mi8: return X86::AND64mi32;
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// OR
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case X86::OR16ri8: return X86::OR16ri;
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case X86::OR16mi8: return X86::OR16mi;
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case X86::OR32ri8: return X86::OR32ri;
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case X86::OR32mi8: return X86::OR32mi;
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case X86::OR64ri8: return X86::OR64ri32;
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case X86::OR64mi8: return X86::OR64mi32;
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// XOR
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case X86::XOR16ri8: return X86::XOR16ri;
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case X86::XOR16mi8: return X86::XOR16mi;
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case X86::XOR32ri8: return X86::XOR32ri;
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case X86::XOR32mi8: return X86::XOR32mi;
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case X86::XOR64ri8: return X86::XOR64ri32;
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case X86::XOR64mi8: return X86::XOR64mi32;
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// ADD
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case X86::ADD16ri8: return X86::ADD16ri;
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case X86::ADD16mi8: return X86::ADD16mi;
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case X86::ADD32ri8: return X86::ADD32ri;
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case X86::ADD32mi8: return X86::ADD32mi;
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case X86::ADD64ri8: return X86::ADD64ri32;
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case X86::ADD64mi8: return X86::ADD64mi32;
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// SUB
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case X86::SUB16ri8: return X86::SUB16ri;
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case X86::SUB16mi8: return X86::SUB16mi;
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case X86::SUB32ri8: return X86::SUB32ri;
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case X86::SUB32mi8: return X86::SUB32mi;
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case X86::SUB64ri8: return X86::SUB64ri32;
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case X86::SUB64mi8: return X86::SUB64mi32;
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// CMP
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case X86::CMP16ri8: return X86::CMP16ri;
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case X86::CMP16mi8: return X86::CMP16mi;
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case X86::CMP32ri8: return X86::CMP32ri;
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case X86::CMP32mi8: return X86::CMP32mi;
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case X86::CMP64ri8: return X86::CMP64ri32;
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case X86::CMP64mi8: return X86::CMP64mi32;
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// PUSH
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case X86::PUSHi8: return X86::PUSHi32;
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case X86::PUSHi16: return X86::PUSHi32;
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case X86::PUSH64i8: return X86::PUSH64i32;
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case X86::PUSH64i16: return X86::PUSH64i32;
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}
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}
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static unsigned getRelaxedOpcode(unsigned Op) {
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unsigned R = getRelaxedOpcodeArith(Op);
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if (R != Op)
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return R;
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return getRelaxedOpcodeBranch(Op);
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}
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bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
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// Branches can always be relaxed.
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if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
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return true;
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if (MCDisableArithRelaxation)
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return false;
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// Check if this instruction is ever relaxable.
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if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
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return false;
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// Check if it has an expression and is not RIP relative.
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bool hasExp = false;
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bool hasRIP = false;
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for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
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const MCOperand &Op = Inst.getOperand(i);
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if (Op.isExpr())
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hasExp = true;
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if (Op.isReg() && Op.getReg() == X86::RIP)
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hasRIP = true;
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}
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// FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
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// how we do relaxations?
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return hasExp && !hasRIP;
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}
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bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCInstFragment *DF,
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const MCAsmLayout &Layout) const {
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// Relax if the value is too big for a (signed) i8.
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return int64_t(Value) != int64_t(int8_t(Value));
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}
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// FIXME: Can tblgen help at all here to verify there aren't other instructions
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// we can relax?
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void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
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// The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
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unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
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if (RelaxedOp == Inst.getOpcode()) {
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SmallString<256> Tmp;
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raw_svector_ostream OS(Tmp);
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Inst.dump_pretty(OS);
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OS << "\n";
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report_fatal_error("unexpected instruction to relax: " + OS.str());
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}
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Res = Inst;
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Res.setOpcode(RelaxedOp);
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}
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/// writeNopData - Write optimal nops to the output file for the \p Count
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/// bytes. This returns the number of bytes written. It may return 0 if
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/// the \p Count is more than the maximum optimal nops.
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bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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static const uint8_t Nops[10][10] = {
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// nop
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{0x90},
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// xchg %ax,%ax
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{0x66, 0x90},
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// nopl (%[re]ax)
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{0x0f, 0x1f, 0x00},
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// nopl 0(%[re]ax)
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{0x0f, 0x1f, 0x40, 0x00},
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// nopl 0(%[re]ax,%[re]ax,1)
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{0x0f, 0x1f, 0x44, 0x00, 0x00},
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// nopw 0(%[re]ax,%[re]ax,1)
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{0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
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// nopl 0L(%[re]ax)
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{0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
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// nopl 0L(%[re]ax,%[re]ax,1)
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{0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
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// nopw 0L(%[re]ax,%[re]ax,1)
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{0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
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// nopw %cs:0L(%[re]ax,%[re]ax,1)
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{0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
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};
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// This CPU doesnt support long nops. If needed add more.
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if (CPU == "geode") {
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for (uint64_t i = 0; i < Count; ++i)
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OW->Write8(0x90);
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return true;
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}
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// Write an optimal sequence for the first 15 bytes.
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const uint64_t OptimalCount = (Count < 16) ? Count : 15;
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const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
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for (uint64_t i = 0, e = Prefixes; i != e; i++)
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OW->Write8(0x66);
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const uint64_t Rest = OptimalCount - Prefixes;
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for (uint64_t i = 0, e = Rest; i != e; i++)
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OW->Write8(Nops[Rest - 1][i]);
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// Finish with single byte nops.
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for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
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OW->Write8(0x90);
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return true;
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}
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/* *** */
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namespace {
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class ELFX86AsmBackend : public X86AsmBackend {
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public:
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uint8_t OSABI;
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ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU)
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: X86AsmBackend(T, CPU), OSABI(_OSABI) {
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HasReliableSymbolDifference = true;
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}
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virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
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const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
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return ES.getFlags() & ELF::SHF_MERGE;
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}
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};
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class ELFX86_32AsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createX86ELFObjectWriter(OS, /*Is64Bit*/ false, OSABI);
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}
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};
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class ELFX86_64AsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createX86ELFObjectWriter(OS, /*Is64Bit*/ true, OSABI);
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}
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};
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class WindowsX86AsmBackend : public X86AsmBackend {
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bool Is64Bit;
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public:
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WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
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: X86AsmBackend(T, CPU)
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, Is64Bit(is64Bit) {
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}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createX86WinCOFFObjectWriter(OS, Is64Bit);
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}
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};
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class DarwinX86AsmBackend : public X86AsmBackend {
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public:
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DarwinX86AsmBackend(const Target &T, StringRef CPU)
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: X86AsmBackend(T, CPU) { }
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};
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class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
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public:
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DarwinX86_32AsmBackend(const Target &T, StringRef CPU)
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: DarwinX86AsmBackend(T, CPU) {}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
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object::mach::CTM_i386,
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object::mach::CSX86_ALL);
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}
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};
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class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
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public:
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DarwinX86_64AsmBackend(const Target &T, StringRef CPU)
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: DarwinX86AsmBackend(T, CPU) {
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HasReliableSymbolDifference = true;
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}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
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object::mach::CTM_x86_64,
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object::mach::CSX86_ALL);
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}
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virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
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// Temporary labels in the string literals sections require symbols. The
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// issue is that the x86_64 relocation format does not allow symbol +
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// offset, and so the linker does not have enough information to resolve the
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// access to the appropriate atom unless an external relocation is used. For
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// non-cstring sections, we expect the compiler to use a non-temporary label
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// for anything that could have an addend pointing outside the symbol.
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//
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// See <rdar://problem/4765733>.
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const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
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return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
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}
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virtual bool isSectionAtomizable(const MCSection &Section) const {
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const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
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// Fixed sized data sections are uniqued, they cannot be diced into atoms.
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switch (SMO.getType()) {
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|
default:
|
|
return true;
|
|
|
|
case MCSectionMachO::S_4BYTE_LITERALS:
|
|
case MCSectionMachO::S_8BYTE_LITERALS:
|
|
case MCSectionMachO::S_16BYTE_LITERALS:
|
|
case MCSectionMachO::S_LITERAL_POINTERS:
|
|
case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
|
|
case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
|
|
case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
|
|
case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
|
|
case MCSectionMachO::S_INTERPOSING:
|
|
return false;
|
|
}
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, StringRef TT, StringRef CPU) {
|
|
Triple TheTriple(TT);
|
|
|
|
if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
|
|
return new DarwinX86_32AsmBackend(T, CPU);
|
|
|
|
if (TheTriple.isOSWindows())
|
|
return new WindowsX86AsmBackend(T, false, CPU);
|
|
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
|
return new ELFX86_32AsmBackend(T, OSABI, CPU);
|
|
}
|
|
|
|
MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT, StringRef CPU) {
|
|
Triple TheTriple(TT);
|
|
|
|
if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
|
|
return new DarwinX86_64AsmBackend(T, CPU);
|
|
|
|
if (TheTriple.isOSWindows())
|
|
return new WindowsX86AsmBackend(T, true, CPU);
|
|
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
|
return new ELFX86_64AsmBackend(T, OSABI, CPU);
|
|
}
|