mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f4fa3d6e46
More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
1.6 KiB
ArmAsm
43 lines
1.6 KiB
ArmAsm
@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s
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.syntax unified
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.globl _func
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@ Check that the assembler can handle the documented syntax from the ARM ARM
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@ for loads and stores.
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_func:
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@ CHECK: _func
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@------------------------------------------------------------------------------
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@ LDR (immediate)
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@------------------------------------------------------------------------------
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ldr r5, [r7]
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ldr r6, [r3, #63]
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ldr r2, [r4, #4095]!
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ldr r1, [r2], #30
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ldr r3, [r1], #-30
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@ CHECK: ldr r5, [r7] @ encoding: [0x00,0x50,0x97,0xe5]
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@ CHECK: ldr r6, [r3, #63] @ encoding: [0x3f,0x60,0x93,0xe5]
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@ CHECK: ldr r2, [r4, #4095]! @ encoding: [0xff,0x2f,0xb4,0xe5]
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@ CHECK: ldr r1, [r2], #30 @ encoding: [0x1e,0x10,0x92,0xe4]
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@ CHECK: ldr r3, [r1], #-30 @ encoding: [0x1e,0x30,0x11,0xe4]
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@------------------------------------------------------------------------------
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@ LDR (register)
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@------------------------------------------------------------------------------
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ldr r3, [r8, r1]
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ldr r2, [r5, -r3]
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ldr r1, [r5, r9]!
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ldr r6, [r7, -r8]!
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ldr r5, [r9], r2
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ldr r4, [r3], -r6
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@ CHECK: ldr r3, [r8, r1] @ encoding: [0x01,0x30,0x98,0xe7]
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@ CHECK: ldr r2, [r5, -r3] @ encoding: [0x03,0x20,0x15,0xe7]
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@ CHECK: ldr r1, [r5, r9]! @ encoding: [0x09,0x10,0xb5,0xe7]
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@ CHECK: ldr r6, [r7, -r8]! @ encoding: [0x08,0x60,0x37,0xe7]
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@ CHECK: ldr r5, [r9], r2 @ encoding: [0x02,0x50,0x99,0xe6]
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@ CHECK: ldr r4, [r3], -r6 @ encoding: [0x06,0x40,0x13,0xe6]
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