Tim Northover f52efce72d ARM: implement MRS/MSR (banked reg) system instructions. ... These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215700 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-15 10:47:12 +00:00
..
Analysis	In LVI(Lazy Value Info), originally value on a BB can only be caculated once,	2014-08-11 05:02:04 +00:00
AsmParser	Canonicalize header guards into a common format.	2014-08-13 16:26:38 +00:00
Bitcode	Canonicalize header guards into a common format.	2014-08-13 16:26:38 +00:00
CodeGen	Revert several FastISel commits to track down a buildbot error.	2014-08-14 19:56:28 +00:00
DebugInfo	Canonicalize header guards into a common format.	2014-08-13 16:26:38 +00:00
ExecutionEngine	[MCJIT] Support DisableSymbolSearching and InstallLazyFunctionCreator in MCJIT.	2014-08-14 02:38:20 +00:00
IR	Canonicalize header guards into a common format.	2014-08-13 16:26:38 +00:00
IRReader	Update the MemoryBuffer API to use ErrorOr.	2014-07-06 17:43:13 +00:00
LineEditor
Linker	Don't upgrade global constructors when reading bitcode	2014-08-12 16:46:37 +00:00
LTO	Don't internalize all but main by default.	2014-08-05 20:10:38 +00:00
MC	Don't print comments to an object streamer :-)	2014-08-15 03:07:13 +00:00
Object	Canonicalize header guards into a common format.	2014-08-13 16:26:38 +00:00
Option	Generic: add range-adapter for option parsing.	2014-07-09 13:03:37 +00:00
ProfileData	Canonicalize header guards into a common format.	2014-08-13 16:26:38 +00:00
Support	Delete support for AuroraUX.	2014-08-14 15:15:09 +00:00
TableGen	Canonicalize header guards into a common format.	2014-08-13 16:26:38 +00:00
Target	ARM: implement MRS/MSR (banked reg) system instructions.	2014-08-15 10:47:12 +00:00
Transforms	Copy noalias metadata from call sites to inlined instructions	2014-08-14 21:09:37 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile