Tim Northover f52efce72d ARM: implement MRS/MSR (banked reg) system instructions. ... These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215700 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-15 10:47:12 +00:00
..
AArch64	MC: AsmLexer: handle multi-character CommentStrings correctly	2014-08-14 02:51:43 +00:00
ARM	ARM: implement MRS/MSR (banked reg) system instructions.	2014-08-15 10:47:12 +00:00
AsmParser	MC: AsmLexer: handle multi-character CommentStrings correctly	2014-08-14 02:51:43 +00:00
COFF	MC: Diagnose an unexpected token in COFF .section instead of asserting	2014-08-11 18:34:43 +00:00
Disassembler	ARM: implement MRS/MSR (banked reg) system instructions.	2014-08-15 10:47:12 +00:00
ELF
MachO	X86: drop relocations on __eh_frame sections globally.	2014-07-22 15:47:09 +00:00
Markup
Mips	Current implementation of c.cond.fmt instructions only accept default cc0 register. This patch enables the instruction to accept other fcc registers. The aliases with default fcc0 registers are also defined.	2014-08-15 09:29:30 +00:00
PowerPC	@l and friends adjust their value depending the context used in.	2014-08-10 12:41:50 +00:00
Sparc
SystemZ	[SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA	2014-07-10 11:00:55 +00:00
X86	[SKX] Extended non-temporal load/store instructions for AVX512VL subsets.	2014-08-13 10:46:00 +00:00