mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-19 17:37:24 +00:00
7da151cd5d
Fixed bug in adjustMipsStackFrame, which was breaking while trying to access a dead stack object index. Also added one more alignment before fixing the callee saved registers stack offset adjustment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54485 91177308-0d34-0410-b5e6-96231b3b80d8
526 lines
18 KiB
C++
526 lines
18 KiB
C++
//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-reg-info"
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "MipsRegisterInfo.h"
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#include "MipsMachineFunction.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
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const TargetInstrInfo &tii)
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: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
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Subtarget(ST), TII(tii) {}
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// Mips::RA, return the number that it corresponds to (e.g. 31).
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unsigned MipsRegisterInfo::
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getRegisterNumbering(unsigned RegEnum)
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{
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switch (RegEnum) {
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case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
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case Mips::AT : case Mips::F1 : return 1;
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case Mips::V0 : case Mips::F2 : case Mips::D1 : return 2;
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case Mips::V1 : case Mips::F3 : return 3;
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case Mips::A0 : case Mips::F4 : case Mips::D2 : return 4;
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case Mips::A1 : case Mips::F5 : return 5;
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case Mips::A2 : case Mips::F6 : case Mips::D3 : return 6;
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case Mips::A3 : case Mips::F7 : return 7;
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case Mips::T0 : case Mips::F8 : case Mips::D4 : return 8;
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case Mips::T1 : case Mips::F9 : return 9;
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case Mips::T2 : case Mips::F10: case Mips::D5: return 10;
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case Mips::T3 : case Mips::F11: return 11;
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case Mips::T4 : case Mips::F12: case Mips::D6: return 12;
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case Mips::T5 : case Mips::F13: return 13;
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case Mips::T6 : case Mips::F14: case Mips::D7: return 14;
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case Mips::T7 : case Mips::F15: return 15;
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case Mips::T8 : case Mips::F16: case Mips::D8: return 16;
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case Mips::T9 : case Mips::F17: return 17;
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case Mips::S0 : case Mips::F18: case Mips::D9: return 18;
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case Mips::S1 : case Mips::F19: return 19;
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case Mips::S2 : case Mips::F20: case Mips::D10: return 20;
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case Mips::S3 : case Mips::F21: return 21;
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case Mips::S4 : case Mips::F22: case Mips::D11: return 22;
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case Mips::S5 : case Mips::F23: return 23;
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case Mips::S6 : case Mips::F24: case Mips::D12: return 24;
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case Mips::S7 : case Mips::F25: return 25;
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case Mips::K0 : case Mips::F26: case Mips::D13: return 26;
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case Mips::K1 : case Mips::F27: return 27;
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case Mips::GP : case Mips::F28: case Mips::D14: return 28;
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case Mips::SP : case Mips::F29: return 29;
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case Mips::FP : case Mips::F30: case Mips::D15: return 30;
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case Mips::RA : case Mips::F31: return 31;
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default: assert(0 && "Unknown register number!");
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}
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return 0; // Not reached
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}
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unsigned MipsRegisterInfo::getPICCallReg(void) { return Mips::T9; }
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//===----------------------------------------------------------------------===//
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// Callee Saved Registers methods
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//===----------------------------------------------------------------------===//
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/// Mips Callee Saved Registers
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const unsigned* MipsRegisterInfo::
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getCalleeSavedRegs(const MachineFunction *MF) const
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{
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// Mips callee-save register range is $16-$23, $f20-$f30
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static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
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Mips::S0, Mips::S1, Mips::S2, Mips::S3,
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Mips::S4, Mips::S5, Mips::S6, Mips::S7,
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Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
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Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
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};
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static const unsigned BitMode32CalleeSavedRegs[] = {
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Mips::S0, Mips::S1, Mips::S2, Mips::S3,
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Mips::S4, Mips::S5, Mips::S6, Mips::S7,
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Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
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Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,0
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};
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if (Subtarget.isSingleFloat())
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return SingleFloatOnlyCalleeSavedRegs;
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else
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return BitMode32CalleeSavedRegs;
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}
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/// Mips Callee Saved Register Classes
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const TargetRegisterClass* const*
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MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
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{
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static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC[] = {
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
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&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
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&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
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&Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
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};
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static const TargetRegisterClass * const BitMode32CalleeSavedRC[] = {
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::AFGR32RegClass, &Mips::AFGR32RegClass, &Mips::AFGR32RegClass,
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&Mips::AFGR32RegClass, &Mips::AFGR32RegClass, &Mips::AFGR32RegClass,
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&Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass,
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&Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, 0
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};
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if (Subtarget.isSingleFloat())
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return SingleFloatOnlyCalleeSavedRC;
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else
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return BitMode32CalleeSavedRC;
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}
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BitVector MipsRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const
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{
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BitVector Reserved(getNumRegs());
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Reserved.set(Mips::ZERO);
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Reserved.set(Mips::AT);
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Reserved.set(Mips::K0);
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Reserved.set(Mips::K1);
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Reserved.set(Mips::GP);
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Reserved.set(Mips::SP);
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Reserved.set(Mips::FP);
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Reserved.set(Mips::RA);
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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//
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// Stack Frame Processing methods
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// +----------------------------+
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//
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// The stack is allocated decrementing the stack pointer on
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// the first instruction of a function prologue. Once decremented,
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// all stack referencesare are done thought a positive offset
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// from the stack/frame pointer, so the stack is considering
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// to grow up! Otherwise terrible hacks would have to be made
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// to get this stack ABI compliant :)
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//
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// The stack frame required by the ABI (after call):
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// Offset
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//
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// 0 ----------
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// 4 Args to pass
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// . saved $GP (used in PIC)
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// . Alloca allocations
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// . Local Area
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// . CPU "Callee Saved" Registers
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// . saved FP
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// . saved RA
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// . FPU "Callee Saved" Registers
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// StackSize -----------
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//
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// Offset - offset from sp after stack allocation on function prologue
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//
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// The sp is the stack pointer subtracted/added from the stack size
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// at the Prologue/Epilogue
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//
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// References to the previous stack (to obtain arguments) are done
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// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
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//
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// Examples:
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// - reference to the actual stack frame
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// for any local area var there is smt like : FI >= 0, StackOffset: 4
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// sw REGX, 4(SP)
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//
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// - reference to previous stack frame
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// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
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// The emitted instruction will be something like:
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// lw REGX, 16+StackSize(SP)
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//
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// Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
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// stack references (ObjectOffset) created to reference the function
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// arguments, are negative numbers. This way, on eliminateFrameIndex it's
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// possible to detect those references and the offsets are adjusted to
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// their real location.
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//
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//===----------------------------------------------------------------------===//
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void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
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{
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
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// Min and Max CSI FrameIndex.
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int MinCSFI = -1, MaxCSFI = -1;
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// See the description at MipsMachineFunction.h
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int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
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// Replace the dummy '0' SPOffset by the negative offsets, as explained on
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// LowerFORMAL_ARGUMENTS. Leaving '0' for while is necessary to avoid
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// the approach done by calculateFrameObjectOffsets to the stack frame.
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MipsFI->adjustLoadArgsFI(MFI);
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MipsFI->adjustStoreVarArgsFI(MFI);
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// It happens that the default stack frame allocation order does not directly
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// map to the convention used for mips. So we must fix it. We move the callee
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// save register slots after the local variables area, as described in the
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// stack frame above.
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unsigned CalleeSavedAreaSize = 0;
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if (!CSI.empty()) {
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MinCSFI = CSI[0].getFrameIdx();
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MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
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}
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for (unsigned i = 0, e = CSI.size(); i != e; ++i)
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CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
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// Adjust local variables. They should come on the stack right
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// after the arguments.
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int LastOffsetFI = -1;
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for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
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if (i >= MinCSFI && i <= MaxCSFI)
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continue;
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if (MFI->isDeadObjectIndex(i))
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continue;
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unsigned Offset = MFI->getObjectOffset(i) - CalleeSavedAreaSize;
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if (LastOffsetFI == -1)
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LastOffsetFI = i;
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if (Offset > MFI->getObjectOffset(LastOffsetFI))
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LastOffsetFI = i;
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MFI->setObjectOffset(i, Offset);
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}
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// Adjust CPU Callee Saved Registers Area. Registers RA and FP must
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// be saved in this CPU Area there is the need. This whole Area must
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// be aligned to the default Stack Alignment requirements.
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unsigned StackOffset = 0;
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unsigned RegSize = Subtarget.isGP32bit() ? 4 : 8;
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if (LastOffsetFI >= 0)
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StackOffset = MFI->getObjectOffset(LastOffsetFI)+
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MFI->getObjectAlignment(LastOffsetFI);
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StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
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for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
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if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass)
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break;
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MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
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TopCPUSavedRegOff = StackOffset;
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StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
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}
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if (hasFP(MF)) {
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MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize),
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StackOffset);
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MipsFI->setFPStackOffset(StackOffset);
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TopCPUSavedRegOff = StackOffset;
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StackOffset += RegSize;
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}
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if (MFI->hasCalls()) {
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MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize),
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StackOffset);
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MipsFI->setRAStackOffset(StackOffset);
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TopCPUSavedRegOff = StackOffset;
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StackOffset += RegSize;
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}
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StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
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// Adjust FPU Callee Saved Registers Area. This Area must be
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// aligned to the default Stack Alignment requirements.
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
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continue;
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MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
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TopFPUSavedRegOff = StackOffset;
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StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
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}
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StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
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// Update frame info
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MFI->setStackSize(StackOffset);
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// Recalculate the final tops offset. The final values must be '0'
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// if there isn't a callee saved register for CPU or FPU, otherwise
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// a negative offset is needed.
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if (TopCPUSavedRegOff >= 0)
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MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
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if (TopFPUSavedRegOff >= 0)
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MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
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}
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool MipsRegisterInfo::
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hasFP(const MachineFunction &MF) const {
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return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
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}
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// This function eliminate ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void MipsRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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void MipsRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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RegScavenger *RS) const
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{
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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unsigned i = 0;
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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#ifndef NDEBUG
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DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
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DOUT << "<--------->\n";
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MI.print(DOUT);
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#endif
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int FrameIndex = MI.getOperand(i).getIndex();
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int stackSize = MF.getFrameInfo()->getStackSize();
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int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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#ifndef NDEBUG
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DOUT << "FrameIndex : " << FrameIndex << "\n";
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DOUT << "spOffset : " << spOffset << "\n";
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DOUT << "stackSize : " << stackSize << "\n";
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#endif
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// as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
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// and adjust SPOffsets considering the final stack size.
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int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
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Offset += MI.getOperand(i-1).getImm();
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#ifndef NDEBUG
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DOUT << "Offset : " << Offset << "\n";
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DOUT << "<--------->\n";
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#endif
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MI.getOperand(i-1).ChangeToImmediate(Offset);
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MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
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}
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void MipsRegisterInfo::
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emitPrologue(MachineFunction &MF) const
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{
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
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// Get the right frame order for Mips.
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adjustMipsStackFrame(MF);
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// Get the number of bytes to allocate from the FrameInfo.
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unsigned StackSize = MFI->getStackSize();
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->hasCalls()) return;
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int FPOffset = MipsFI->getFPStackOffset();
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int RAOffset = MipsFI->getRAStackOffset();
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BuildMI(MBB, MBBI, TII.get(Mips::NOREORDER));
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// TODO: check need from GP here.
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if (isPIC && Subtarget.isABI_O32())
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BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
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BuildMI(MBB, MBBI, TII.get(Mips::NOMACRO));
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// Adjust stack : addi sp, sp, (-imm)
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BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(-StackSize);
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// Save the return address only if the function isnt a leaf one.
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// sw $ra, stack_loc($sp)
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if (MFI->hasCalls()) {
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BuildMI(MBB, MBBI, TII.get(Mips::SW))
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.addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
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}
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// if framepointer enabled, save it and set it
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// to point to the stack pointer
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if (hasFP(MF)) {
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// sw $fp,stack_loc($sp)
|
|
BuildMI(MBB, MBBI, TII.get(Mips::SW))
|
|
.addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
|
|
|
|
// move $fp, $sp
|
|
BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
|
|
.addReg(Mips::SP).addReg(Mips::ZERO);
|
|
}
|
|
|
|
// PIC speficic function prologue
|
|
if ((isPIC) && (MFI->hasCalls())) {
|
|
BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
|
|
.addImm(MipsFI->getGPStackOffset());
|
|
}
|
|
}
|
|
|
|
void MipsRegisterInfo::
|
|
emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
|
|
{
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
// Get the number of bytes from FrameInfo
|
|
int NumBytes = (int) MFI->getStackSize();
|
|
|
|
// Get the FI's where RA and FP are saved.
|
|
int FPOffset = MipsFI->getFPStackOffset();
|
|
int RAOffset = MipsFI->getRAStackOffset();
|
|
|
|
// if framepointer enabled, restore it and restore the
|
|
// stack pointer
|
|
if (hasFP(MF)) {
|
|
// move $sp, $fp
|
|
BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
|
|
.addReg(Mips::FP).addReg(Mips::ZERO);
|
|
|
|
// lw $fp,stack_loc($sp)
|
|
BuildMI(MBB, MBBI, TII.get(Mips::LW))
|
|
.addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
|
|
}
|
|
|
|
// Restore the return address only if the function isnt a leaf one.
|
|
// lw $ra, stack_loc($sp)
|
|
if (MFI->hasCalls()) {
|
|
BuildMI(MBB, MBBI, TII.get(Mips::LW))
|
|
.addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
|
|
}
|
|
|
|
// adjust stack : insert addi sp, sp, (imm)
|
|
if (NumBytes) {
|
|
BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
|
|
.addReg(Mips::SP).addImm(NumBytes);
|
|
}
|
|
}
|
|
|
|
|
|
void MipsRegisterInfo::
|
|
processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
|
|
// Set the SPOffset on the FI where GP must be saved/loaded.
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
|
|
if (MFI->hasCalls() && isPIC) {
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
|
|
}
|
|
}
|
|
|
|
unsigned MipsRegisterInfo::
|
|
getRARegister() const {
|
|
return Mips::RA;
|
|
}
|
|
|
|
unsigned MipsRegisterInfo::
|
|
getFrameRegister(MachineFunction &MF) const {
|
|
return hasFP(MF) ? Mips::FP : Mips::SP;
|
|
}
|
|
|
|
unsigned MipsRegisterInfo::
|
|
getEHExceptionRegister() const {
|
|
assert(0 && "What is the exception register");
|
|
return 0;
|
|
}
|
|
|
|
unsigned MipsRegisterInfo::
|
|
getEHHandlerRegister() const {
|
|
assert(0 && "What is the exception handler register");
|
|
return 0;
|
|
}
|
|
|
|
int MipsRegisterInfo::
|
|
getDwarfRegNum(unsigned RegNum, bool isEH) const {
|
|
assert(0 && "What is the dwarf register number");
|
|
return -1;
|
|
}
|
|
|
|
#include "MipsGenRegisterInfo.inc"
|
|
|