mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224075 91177308-0d34-0410-b5e6-96231b3b80d8
310 lines
12 KiB
C++
310 lines
12 KiB
C++
//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64TargetMachine.h"
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#include "AArch64TargetObjectFile.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/IR/Function.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl::opt<bool>
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EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool> EnableMCR("aarch64-mcr",
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cl::desc("Enable the machine combiner pass"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
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" integer instructions"), cl::init(false), cl::Hidden);
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static cl::opt<bool>
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EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
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"constant pass"), cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
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" linker optimization hints (LOH)"), cl::init(true),
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cl::Hidden);
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static cl::opt<bool>
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EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
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cl::desc("Enable the pass that removes dead"
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" definitons and replaces stores to"
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" them with stores to the zero"
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" register"),
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cl::init(true));
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static cl::opt<bool>
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EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
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" optimization pass"), cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
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cl::desc("Run SimplifyCFG after expanding atomic operations"
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" to make use of cmpxchg flow-based information"),
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cl::init(true));
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static cl::opt<bool>
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EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
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cl::desc("Run early if-conversion"),
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cl::init(true));
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static cl::opt<bool>
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EnableCondOpt("aarch64-condopt",
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cl::desc("Enable the condition optimizer pass"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
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cl::desc("Work around Cortex-A53 erratum 835769"),
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cl::init(false));
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static cl::opt<bool>
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EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
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cl::desc("Enable optimizations on complex GEPs"),
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cl::init(true));
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extern "C" void LLVMInitializeAArch64Target() {
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// Register the target.
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RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
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RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
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RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
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}
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//===----------------------------------------------------------------------===//
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// AArch64 Lowering public interface.
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//===----------------------------------------------------------------------===//
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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if (TT.isOSBinFormatMachO())
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return make_unique<AArch64_MachoTargetObjectFile>();
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return make_unique<AArch64_ELFTargetObjectFile>();
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}
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/// TargetMachine ctor - Create an AArch64 architecture model.
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///
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AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool LittleEndian)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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TLOF(createTLOF(Triple(getTargetTriple()))),
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Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
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initAsmInfo();
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}
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AArch64TargetMachine::~AArch64TargetMachine() {}
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const AArch64Subtarget *
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AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
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AttributeSet FnAttrs = F.getAttributes();
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Attribute CPUAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
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Attribute FSAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
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}
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return I.get();
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}
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void AArch64leTargetMachine::anchor() { }
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AArch64leTargetMachine::
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AArch64leTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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void AArch64beTargetMachine::anchor() { }
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AArch64beTargetMachine::
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AArch64beTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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namespace {
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/// AArch64 Code Generator Pass Configuration Options.
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class AArch64PassConfig : public TargetPassConfig {
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public:
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AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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if (TM->getOptLevel() != CodeGenOpt::None)
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substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
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}
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AArch64TargetMachine &getAArch64TargetMachine() const {
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return getTM<AArch64TargetMachine>();
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}
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void addIRPasses() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addILPOpts() override;
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void addPreRegAlloc() override;
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void addPostRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // namespace
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void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our AArch64 pass. This
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// allows the AArch64 pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createAArch64TargetTransformInfoPass(this));
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}
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TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new AArch64PassConfig(this, PM);
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}
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void AArch64PassConfig::addIRPasses() {
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// Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
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// ourselves.
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addPass(createAtomicExpandPass(TM));
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// Cmpxchg instructions are often used with a subsequent comparison to
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// determine whether it succeeded. We can exploit existing control-flow in
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// ldrex/strex loops to simplify this, but it needs tidying up.
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if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
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addPass(createCFGSimplificationPass());
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TargetPassConfig::addIRPasses();
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if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
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// Call SeparateConstOffsetFromGEP pass to extract constants within indices
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// and lower a GEP with multiple indices to either arithmetic operations or
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// multiple GEPs with single index.
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addPass(createSeparateConstOffsetFromGEPPass(TM, true));
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// Call EarlyCSE pass to find and remove subexpressions in the lowered
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// result.
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addPass(createEarlyCSEPass());
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// Do loop invariant code motion in case part of the lowered result is
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// invariant.
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addPass(createLICMPass());
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}
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}
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// Pass Pipeline Configuration
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bool AArch64PassConfig::addPreISel() {
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// Run promote constant before global merge, so that the promoted constants
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// get a chance to be merged
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if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
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addPass(createAArch64PromoteConstantPass());
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if (TM->getOptLevel() != CodeGenOpt::None)
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addPass(createGlobalMergePass(TM));
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if (TM->getOptLevel() != CodeGenOpt::None)
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addPass(createAArch64AddressTypePromotionPass());
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return false;
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}
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bool AArch64PassConfig::addInstSelector() {
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addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
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// For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
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// references to _TLS_MODULE_BASE_ as possible.
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if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
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getOptLevel() != CodeGenOpt::None)
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addPass(createAArch64CleanupLocalDynamicTLSPass());
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return false;
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}
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bool AArch64PassConfig::addILPOpts() {
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if (EnableCondOpt)
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addPass(createAArch64ConditionOptimizerPass());
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if (EnableCCMP)
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addPass(createAArch64ConditionalCompares());
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if (EnableMCR)
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addPass(&MachineCombinerID);
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if (EnableEarlyIfConversion)
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addPass(&EarlyIfConverterID);
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if (EnableStPairSuppress)
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addPass(createAArch64StorePairSuppressPass());
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return true;
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}
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void AArch64PassConfig::addPreRegAlloc() {
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// Use AdvSIMD scalar instructions whenever profitable.
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if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
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addPass(createAArch64AdvSIMDScalar());
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// The AdvSIMD pass may produce copies that can be rewritten to
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// be register coaleascer friendly.
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addPass(&PeepholeOptimizerID);
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}
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}
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void AArch64PassConfig::addPostRegAlloc() {
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// Change dead register definitions to refer to the zero register.
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if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
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addPass(createAArch64DeadRegisterDefinitions());
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if (TM->getOptLevel() != CodeGenOpt::None &&
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(TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
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TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
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usingDefaultRegAlloc())
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// Improve performance for some FP/SIMD code for A57.
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addPass(createAArch64A57FPLoadBalancing());
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}
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void AArch64PassConfig::addPreSched2() {
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// Expand some pseudo instructions to allow proper scheduling.
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addPass(createAArch64ExpandPseudoPass());
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// Use load/store pair instructions when possible.
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if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
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addPass(createAArch64LoadStoreOptimizationPass());
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}
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void AArch64PassConfig::addPreEmitPass() {
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if (EnableA53Fix835769)
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addPass(createAArch64A53Fix835769());
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// Relax conditional branch instructions if they're otherwise out of
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// range of their destination.
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addPass(createAArch64BranchRelaxation());
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if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
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TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
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addPass(createAArch64CollectLOHPass());
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}
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