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00e08fcaa0
Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215558 91177308-0d34-0410-b5e6-96231b3b80d8
239 lines
7.2 KiB
C++
239 lines
7.2 KiB
C++
//===-- MipsABIFlagsSection.h - Mips ELF ABI Flags Section -----*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
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#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
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#include "llvm/MC/MCStreamer.h"
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namespace llvm {
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class MCStreamer;
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struct MipsABIFlagsSection {
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// Values for the xxx_size bytes of an ABI flags structure.
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enum AFL_REG {
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AFL_REG_NONE = 0x00, // No registers.
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AFL_REG_32 = 0x01, // 32-bit registers.
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AFL_REG_64 = 0x02, // 64-bit registers.
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AFL_REG_128 = 0x03 // 128-bit registers.
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};
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// Masks for the ases word of an ABI flags structure.
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enum AFL_ASE {
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AFL_ASE_DSP = 0x00000001, // DSP ASE.
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AFL_ASE_DSPR2 = 0x00000002, // DSP R2 ASE.
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AFL_ASE_EVA = 0x00000004, // Enhanced VA Scheme.
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AFL_ASE_MCU = 0x00000008, // MCU (MicroController) ASE.
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AFL_ASE_MDMX = 0x00000010, // MDMX ASE.
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AFL_ASE_MIPS3D = 0x00000020, // MIPS-3D ASE.
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AFL_ASE_MT = 0x00000040, // MT ASE.
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AFL_ASE_SMARTMIPS = 0x00000080, // SmartMIPS ASE.
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AFL_ASE_VIRT = 0x00000100, // VZ ASE.
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AFL_ASE_MSA = 0x00000200, // MSA ASE.
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AFL_ASE_MIPS16 = 0x00000400, // MIPS16 ASE.
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AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE.
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AFL_ASE_XPA = 0x00001000 // XPA ASE.
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};
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// Values for the isa_ext word of an ABI flags structure.
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enum AFL_EXT {
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AFL_EXT_XLR = 1, // RMI Xlr instruction.
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AFL_EXT_OCTEON2 = 2, // Cavium Networks Octeon2.
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AFL_EXT_OCTEONP = 3, // Cavium Networks OcteonP.
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AFL_EXT_LOONGSON_3A = 4, // Loongson 3A.
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AFL_EXT_OCTEON = 5, // Cavium Networks Octeon.
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AFL_EXT_5900 = 6, // MIPS R5900 instruction.
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AFL_EXT_4650 = 7, // MIPS R4650 instruction.
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AFL_EXT_4010 = 8, // LSI R4010 instruction.
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AFL_EXT_4100 = 9, // NEC VR4100 instruction.
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AFL_EXT_3900 = 10, // Toshiba R3900 instruction.
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AFL_EXT_10000 = 11, // MIPS R10000 instruction.
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AFL_EXT_SB1 = 12, // Broadcom SB-1 instruction.
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AFL_EXT_4111 = 13, // NEC VR4111/VR4181 instruction.
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AFL_EXT_4120 = 14, // NEC VR4120 instruction.
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AFL_EXT_5400 = 15, // NEC VR5400 instruction.
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AFL_EXT_5500 = 16, // NEC VR5500 instruction.
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AFL_EXT_LOONGSON_2E = 17, // ST Microelectronics Loongson 2E.
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AFL_EXT_LOONGSON_2F = 18 // ST Microelectronics Loongson 2F.
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};
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// Values for the fp_abi word of an ABI flags structure.
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enum Val_GNU_MIPS_ABI {
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Val_GNU_MIPS_ABI_FP_ANY = 0,
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Val_GNU_MIPS_ABI_FP_DOUBLE = 1,
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Val_GNU_MIPS_ABI_FP_XX = 5,
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Val_GNU_MIPS_ABI_FP_64 = 6,
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Val_GNU_MIPS_ABI_FP_64A = 7
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};
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enum AFL_FLAGS1 {
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AFL_FLAGS1_ODDSPREG = 1
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};
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// Internal representation of the values used in .module fp=value
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enum class FpABIKind { ANY, XX, S32, S64 };
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// Version of flags structure.
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uint16_t Version;
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// The level of the ISA: 1-5, 32, 64.
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uint8_t ISALevel;
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// The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
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uint8_t ISARevision;
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// The size of general purpose registers.
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AFL_REG GPRSize;
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// The size of co-processor 1 registers.
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AFL_REG CPR1Size;
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// The size of co-processor 2 registers.
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AFL_REG CPR2Size;
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// Processor-specific extension.
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uint32_t ISAExtensionSet;
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// Mask of ASEs used.
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uint32_t ASESet;
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bool OddSPReg;
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bool Is32BitABI;
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protected:
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// The floating-point ABI.
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FpABIKind FpABI;
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public:
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MipsABIFlagsSection()
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: Version(0), ISALevel(0), ISARevision(0), GPRSize(AFL_REG_NONE),
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CPR1Size(AFL_REG_NONE), CPR2Size(AFL_REG_NONE), ISAExtensionSet(0),
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ASESet(0), OddSPReg(false), Is32BitABI(false), FpABI(FpABIKind::ANY) {}
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uint16_t getVersionValue() { return (uint16_t)Version; }
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uint8_t getISALevelValue() { return (uint8_t)ISALevel; }
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uint8_t getISARevisionValue() { return (uint8_t)ISARevision; }
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uint8_t getGPRSizeValue() { return (uint8_t)GPRSize; }
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uint8_t getCPR1SizeValue();
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uint8_t getCPR2SizeValue() { return (uint8_t)CPR2Size; }
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uint8_t getFpABIValue();
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uint32_t getISAExtensionSetValue() { return (uint32_t)ISAExtensionSet; }
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uint32_t getASESetValue() { return (uint32_t)ASESet; }
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uint32_t getFlags1Value() {
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uint32_t Value = 0;
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if (OddSPReg)
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Value |= (uint32_t)AFL_FLAGS1_ODDSPREG;
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return Value;
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}
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uint32_t getFlags2Value() { return 0; }
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FpABIKind getFpABI() { return FpABI; }
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void setFpABI(FpABIKind Value, bool IsABI32Bit) {
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FpABI = Value;
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Is32BitABI = IsABI32Bit;
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}
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StringRef getFpABIString(FpABIKind Value);
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template <class PredicateLibrary>
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void setISALevelAndRevisionFromPredicates(const PredicateLibrary &P) {
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if (P.hasMips64()) {
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ISALevel = 64;
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if (P.hasMips64r6())
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ISARevision = 6;
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else if (P.hasMips64r2())
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ISARevision = 2;
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else
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ISARevision = 1;
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} else if (P.hasMips32()) {
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ISALevel = 32;
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if (P.hasMips32r6())
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ISARevision = 6;
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else if (P.hasMips32r2())
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ISARevision = 2;
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else
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ISARevision = 1;
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} else {
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ISARevision = 0;
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if (P.hasMips5())
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ISALevel = 5;
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else if (P.hasMips4())
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ISALevel = 4;
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else if (P.hasMips3())
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ISALevel = 3;
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else if (P.hasMips2())
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ISALevel = 2;
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else if (P.hasMips1())
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ISALevel = 1;
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else
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llvm_unreachable("Unknown ISA level!");
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}
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}
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template <class PredicateLibrary>
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void setGPRSizeFromPredicates(const PredicateLibrary &P) {
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GPRSize = P.isGP64bit() ? AFL_REG_64 : AFL_REG_32;
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}
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template <class PredicateLibrary>
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void setCPR1SizeFromPredicates(const PredicateLibrary &P) {
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if (P.abiUsesSoftFloat())
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CPR1Size = AFL_REG_NONE;
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else if (P.hasMSA())
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CPR1Size = AFL_REG_128;
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else
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CPR1Size = P.isFP64bit() ? AFL_REG_64 : AFL_REG_32;
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}
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template <class PredicateLibrary>
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void setASESetFromPredicates(const PredicateLibrary &P) {
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ASESet = 0;
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if (P.hasDSP())
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ASESet |= AFL_ASE_DSP;
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if (P.hasDSPR2())
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ASESet |= AFL_ASE_DSPR2;
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if (P.hasMSA())
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ASESet |= AFL_ASE_MSA;
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if (P.inMicroMipsMode())
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ASESet |= AFL_ASE_MICROMIPS;
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if (P.inMips16Mode())
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ASESet |= AFL_ASE_MIPS16;
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}
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template <class PredicateLibrary>
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void setFpAbiFromPredicates(const PredicateLibrary &P) {
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Is32BitABI = P.isABI_O32();
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FpABI = FpABIKind::ANY;
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if (P.isABI_N32() || P.isABI_N64())
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FpABI = FpABIKind::S64;
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else if (P.isABI_O32()) {
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if (P.isABI_FPXX())
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FpABI = FpABIKind::XX;
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else if (P.isFP64bit())
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FpABI = FpABIKind::S64;
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else
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FpABI = FpABIKind::S32;
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}
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}
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template <class PredicateLibrary>
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void setAllFromPredicates(const PredicateLibrary &P) {
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setISALevelAndRevisionFromPredicates(P);
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setGPRSizeFromPredicates(P);
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setCPR1SizeFromPredicates(P);
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setASESetFromPredicates(P);
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setFpAbiFromPredicates(P);
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OddSPReg = P.useOddSPReg();
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}
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};
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MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection);
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}
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#endif
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