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ed788b6283
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8
12 lines
436 B
LLVM
12 lines
436 B
LLVM
; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic < %s
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; This isn't exactly a useful set of command-line options, but check that it
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; doesn't crash. (It was crashing because a register was getting redefined.)
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target triple = "thumbv7-apple-macosx10.6.7"
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define i32 @f(i32* %x) nounwind ssp {
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%y = getelementptr inbounds i32* %x, i32 5000
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%tmp103 = load i32* %y, align 4
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ret i32 %tmp103
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}
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