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https://github.com/c64scene-ar/llvm-6502.git
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1c6611db44
The current peephole optimizing for compare inst assumes an instr that uses CPSR has an MO for ARM Cond code.However, for VSEL instructions (vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do they support the modification of Cond Code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196588 91177308-0d34-0410-b5e6-96231b3b80d8
147 lines
3.3 KiB
LLVM
147 lines
3.3 KiB
LLVM
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7
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; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8
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define i32 @f(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: f:
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; CHECK: subs
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; CHECK-NOT: cmp
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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define i32 @g(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: g:
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; CHECK: subs
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; CHECK-NOT: cmp
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%cmp = icmp slt i32 %a, %b
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%sub = sub nsw i32 %b, %a
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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define i32 @h(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: h:
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; CHECK: subs
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; CHECK-NOT: cmp
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%cmp = icmp sgt i32 %a, 3
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%sub = sub nsw i32 %a, 3
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%sub. = select i1 %cmp, i32 %sub, i32 %b
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ret i32 %sub.
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}
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; rdar://11725965
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define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: i:
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; CHECK: subs
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; CHECK-NOT: cmp
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%cmp = icmp ult i32 %a, %b
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%sub = sub i32 %b, %a
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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; If CPSR is live-out, we can't remove cmp if there exists
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; a swapped sub.
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define i32 @j(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: j:
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; CHECK: sub
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; CHECK: cmp
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%cmp = icmp eq i32 %b, %a
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%sub = sub nsw i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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%cmp2 = icmp sgt i32 %b, %a
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%sel = select i1 %cmp2, i32 %sub, i32 %a
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ret i32 %sel
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if.else:
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ret i32 %sub
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}
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; If the sub/rsb instruction is predicated, we can't use the flags.
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; <rdar://problem/12263428>
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; Test case from MultiSource/Benchmarks/Ptrdist/bc/number.s
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; CHECK: bc_raise
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; CHECK: rsbeq
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; CHECK: cmp
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define i32 @bc_raise() nounwind ssp {
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entry:
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%val.2.i = select i1 undef, i32 0, i32 undef
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%sub.i = sub nsw i32 0, %val.2.i
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%retval.0.i = select i1 undef, i32 %val.2.i, i32 %sub.i
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%cmp1 = icmp eq i32 %retval.0.i, 0
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br i1 %cmp1, label %land.lhs.true, label %if.end11
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land.lhs.true: ; preds = %num2long.exit
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ret i32 17
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if.end11: ; preds = %num2long.exit
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ret i32 23
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}
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define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
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entry:
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; CHECK-LABEL: float_sel:
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; CHECK-NOT: cmp
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; V8-LABEL: float_sel:
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; V8-NOT: cmp
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; V8: vseleq.f32
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%sub = sub i32 %a, %b
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%cmp = icmp eq i32 %sub, 0
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%ret = select i1 %cmp, float %x, float %y
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ret float %ret
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}
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define double @double_sel(i32 %a, i32 %b, double %x, double %y) {
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entry:
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; CHECK-LABEL: double_sel:
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; CHECK-NOT: cmp
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; V8-LABEL: double_sel:
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; V8-NOT: cmp
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; V8: vseleq.f64
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%sub = sub i32 %a, %b
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%cmp = icmp eq i32 %sub, 0
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%ret = select i1 %cmp, double %x, double %y
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ret double %ret
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}
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@t = common global i32 0
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define double @double_sub(i32 %a, i32 %b, double %x, double %y) {
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entry:
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; CHECK-LABEL: double_sub:
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; CHECK: subs
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; CHECK-NOT: cmp
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; V8-LABEL: double_sub:
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; V8: vsel
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%cmp = icmp sgt i32 %a, %b
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%sub = sub i32 %a, %b
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store i32 %sub, i32* @t
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%ret = select i1 %cmp, double %x, double %y
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ret double %ret
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}
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define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) {
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entry:
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; V7-LABEL: double_sub_swap:
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; V7-NOT: cmp
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; V7: subs
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; V8-LABEL: double_sub_swap:
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; V8-NOT: subs
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; V8: cmp
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; V8: vsel
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%cmp = icmp sgt i32 %a, %b
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%sub = sub i32 %b, %a
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%ret = select i1 %cmp, double %x, double %y
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store i32 %sub, i32* @t
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ret double %ret
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}
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