mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-01 19:29:22 +00:00
c0021e43ea
This is a union of these commits:
* R600/SI: Enable more tests for VI which need no changes
* R600/SI: Enable V_BCNT tests for VI
Differences:
- v_bcnt_..._e32 -> _e64
- s_load_dword* inline offset is in bytes instead of dwords
* R600/SI: Enable all tests for VI which use S_LOAD_DWORD
The inline offset is changed from dwords to bytes.
* R600/SI: Enable LDS tests for VI
Differences:
- the s_load_dword inline offset changed from dwords to bytes
- the tests checked very little on CI, so they have been fixed to check all
instructions that "SI" checked
* R600/SI: Enable lshr tests for VI
* R600/SI: Fix divrem64 tests
- "v_lshl_64" was missing "b" before "64"
- added VI-NOT checks
* R600/SI: Enable the SI.tid test for VI
* R600/SI: Enable the frem test for VI
Also, the frem_f64 checking is added for CI-VI.
* R600/SI: Add VI tests for rsq.clamped
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228830 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
4.6 KiB
LLVM
115 lines
4.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -enable-misched < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -enable-misched < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -enable-misched < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}frem_f32:
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; GCN-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}}
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; GCN-DAG: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
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; GCN-DAG: v_cmp
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; GCN-DAG: v_mul_f32
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; GCN: v_rcp_f32_e32
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; GCN: v_mul_f32_e32
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; GCN: v_mul_f32_e32
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; GCN: v_trunc_f32_e32
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; GCN: v_mad_f32
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; GCN: s_endpgm
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define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2) #0 {
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%gep2 = getelementptr float addrspace(1)* %in2, i32 4
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%r0 = load float addrspace(1)* %in1, align 4
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%r1 = load float addrspace(1)* %gep2, align 4
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%r2 = frem float %r0, %r1
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store float %r2, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_frem_f32:
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; GCN: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
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; GCN: buffer_load_dword [[X:v[0-9]+]], {{.*}}
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; GCN: v_rcp_f32_e32 [[INVY:v[0-9]+]], [[Y]]
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; GCN: v_mul_f32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]]
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; GCN: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[DIV]]
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; GCN: v_mad_f32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]]
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; GCN: buffer_store_dword [[RESULT]]
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; GCN: s_endpgm
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define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2) #1 {
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%gep2 = getelementptr float addrspace(1)* %in2, i32 4
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%r0 = load float addrspace(1)* %in1, align 4
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%r1 = load float addrspace(1)* %gep2, align 4
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%r2 = frem float %r0, %r1
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store float %r2, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}frem_f64:
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; GCN: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], {{.*}}, 0
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; GCN: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], {{.*}}, 0
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; TODO: Check SI.
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; CI: v_rcp_f64_e32 [[INVY:v\[[0-9]+:[0-9]+\]]], [[Y]]
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; CI: v_mul_f64 [[DIV:v\[[0-9]+:[0-9]+\]]], [[X]], [[INVY]]
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; CI: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[DIV]]
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; CI: v_mul_f64 [[RESULTM:v\[[0-9]+:[0-9]+\]]], [[TRUNC]], [[Y]]
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; SI: v_mul_f64 [[RESULTM:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, [[Y]]
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; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[X]], -[[RESULTM]]
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; GCN: buffer_store_dwordx2 [[RESULT]], {{.*}}, 0
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; GCN: s_endpgm
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define void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) #0 {
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%r0 = load double addrspace(1)* %in1, align 8
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%r1 = load double addrspace(1)* %in2, align 8
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%r2 = frem double %r0, %r1
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store double %r2, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_frem_f64:
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; GCN: v_rcp_f64_e32
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; GCN: v_mul_f64
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; SI: v_bfe_u32
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; CI: v_trunc_f64_e32
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; GCN: v_fma_f64
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; GCN: s_endpgm
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define void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) #1 {
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%r0 = load double addrspace(1)* %in1, align 8
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%r1 = load double addrspace(1)* %in2, align 8
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%r2 = frem double %r0, %r1
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store double %r2, double addrspace(1)* %out, align 8
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ret void
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}
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define void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
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<2 x float> addrspace(1)* %in2) #0 {
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%gep2 = getelementptr <2 x float> addrspace(1)* %in2, i32 4
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%r0 = load <2 x float> addrspace(1)* %in1, align 8
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%r1 = load <2 x float> addrspace(1)* %gep2, align 8
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%r2 = frem <2 x float> %r0, %r1
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store <2 x float> %r2, <2 x float> addrspace(1)* %out, align 8
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ret void
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}
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define void @frem_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
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<4 x float> addrspace(1)* %in2) #0 {
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%gep2 = getelementptr <4 x float> addrspace(1)* %in2, i32 4
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%r0 = load <4 x float> addrspace(1)* %in1, align 16
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%r1 = load <4 x float> addrspace(1)* %gep2, align 16
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%r2 = frem <4 x float> %r0, %r1
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store <4 x float> %r2, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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define void @frem_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
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<2 x double> addrspace(1)* %in2) #0 {
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%gep2 = getelementptr <2 x double> addrspace(1)* %in2, i32 4
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%r0 = load <2 x double> addrspace(1)* %in1, align 16
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%r1 = load <2 x double> addrspace(1)* %gep2, align 16
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%r2 = frem <2 x double> %r0, %r1
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store <2 x double> %r2, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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attributes #0 = { nounwind "unsafe-fp-math"="false" }
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attributes #1 = { nounwind "unsafe-fp-math"="true" }
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