mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165416 91177308-0d34-0410-b5e6-96231b3b80d8
1278 lines
43 KiB
C++
1278 lines
43 KiB
C++
//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// MachineScheduler schedules machine instructions after phi elimination. It
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// preserves LiveIntervals so it can be invoked before register allocation.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "misched"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/PriorityQueue.h"
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#include <queue>
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using namespace llvm;
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namespace llvm {
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cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
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cl::desc("Force top-down list scheduling"));
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cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
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cl::desc("Force bottom-up list scheduling"));
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}
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#ifndef NDEBUG
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static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
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cl::desc("Pop up a window to show MISched dags after they are processed"));
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static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
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cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
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#else
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static bool ViewMISchedDAGs = false;
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#endif // NDEBUG
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//===----------------------------------------------------------------------===//
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// Machine Instruction Scheduling Pass and Registry
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//===----------------------------------------------------------------------===//
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MachineSchedContext::MachineSchedContext():
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MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
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RegClassInfo = new RegisterClassInfo();
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}
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MachineSchedContext::~MachineSchedContext() {
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delete RegClassInfo;
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}
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namespace {
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/// MachineScheduler runs after coalescing and before register allocation.
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class MachineScheduler : public MachineSchedContext,
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public MachineFunctionPass {
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public:
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MachineScheduler();
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory() {}
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virtual bool runOnMachineFunction(MachineFunction&);
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virtual void print(raw_ostream &O, const Module* = 0) const;
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static char ID; // Class identification, replacement for typeinfo
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};
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} // namespace
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char MachineScheduler::ID = 0;
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char &llvm::MachineSchedulerID = MachineScheduler::ID;
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INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
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"Machine Instruction Scheduler", false, false)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(MachineScheduler, "misched",
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"Machine Instruction Scheduler", false, false)
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MachineScheduler::MachineScheduler()
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: MachineFunctionPass(ID) {
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initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
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}
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void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequiredID(MachineDominatorsID);
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<TargetPassConfig>();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachinePassRegistry MachineSchedRegistry::Registry;
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/// A dummy default scheduler factory indicates whether the scheduler
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/// is overridden on the command line.
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static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
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return 0;
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}
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/// MachineSchedOpt allows command line selection of the scheduler.
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static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
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RegisterPassParser<MachineSchedRegistry> >
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MachineSchedOpt("misched",
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cl::init(&useDefaultMachineSched), cl::Hidden,
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cl::desc("Machine instruction scheduler to use"));
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static MachineSchedRegistry
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DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
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useDefaultMachineSched);
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/// Forward declare the standard machine scheduler. This will be used as the
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/// default scheduler if the target does not set a default.
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static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C);
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/// Decrement this iterator until reaching the top or a non-debug instr.
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static MachineBasicBlock::iterator
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priorNonDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator Beg) {
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assert(I != Beg && "reached the top of the region, cannot decrement");
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while (--I != Beg) {
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if (!I->isDebugValue())
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break;
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}
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return I;
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}
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/// If this iterator is a debug value, increment until reaching the End or a
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/// non-debug instruction.
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static MachineBasicBlock::iterator
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nextIfDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator End) {
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for(; I != End; ++I) {
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if (!I->isDebugValue())
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break;
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}
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return I;
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}
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/// Top-level MachineScheduler pass driver.
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///
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/// Visit blocks in function order. Divide each block into scheduling regions
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/// and visit them bottom-up. Visiting regions bottom-up is not required, but is
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/// consistent with the DAG builder, which traverses the interior of the
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/// scheduling regions bottom-up.
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///
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/// This design avoids exposing scheduling boundaries to the DAG builder,
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/// simplifying the DAG builder's support for "special" target instructions.
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/// At the same time the design allows target schedulers to operate across
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/// scheduling boundaries, for example to bundle the boudary instructions
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/// without reordering them. This creates complexity, because the target
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/// scheduler must update the RegionBegin and RegionEnd positions cached by
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/// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
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/// design would be to split blocks at scheduling boundaries, but LLVM has a
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/// general bias against block splitting purely for implementation simplicity.
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bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
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DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
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// Initialize the context of the pass.
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MF = &mf;
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MLI = &getAnalysis<MachineLoopInfo>();
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MDT = &getAnalysis<MachineDominatorTree>();
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PassConfig = &getAnalysis<TargetPassConfig>();
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AA = &getAnalysis<AliasAnalysis>();
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LIS = &getAnalysis<LiveIntervals>();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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RegClassInfo->runOnMachineFunction(*MF);
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// Select the scheduler, or set the default.
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MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
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if (Ctor == useDefaultMachineSched) {
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// Get the default scheduler set by the target.
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Ctor = MachineSchedRegistry::getDefault();
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if (!Ctor) {
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Ctor = createConvergingSched;
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MachineSchedRegistry::setDefault(Ctor);
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}
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}
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// Instantiate the selected scheduler.
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OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
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// Visit all machine basic blocks.
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//
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// TODO: Visit blocks in global postorder or postorder within the bottom-up
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// loop tree. Then we can optionally compute global RegPressure.
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for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
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MBB != MBBEnd; ++MBB) {
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Scheduler->startBlock(MBB);
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// Break the block into scheduling regions [I, RegionEnd), and schedule each
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// region as soon as it is discovered. RegionEnd points the scheduling
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// boundary at the bottom of the region. The DAG does not include RegionEnd,
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// but the region does (i.e. the next RegionEnd is above the previous
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// RegionBegin). If the current block has no terminator then RegionEnd ==
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// MBB->end() for the bottom region.
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//
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// The Scheduler may insert instructions during either schedule() or
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// exitRegion(), even for empty regions. So the local iterators 'I' and
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// 'RegionEnd' are invalid across these calls.
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unsigned RemainingCount = MBB->size();
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for(MachineBasicBlock::iterator RegionEnd = MBB->end();
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RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
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// Avoid decrementing RegionEnd for blocks with no terminator.
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if (RegionEnd != MBB->end()
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|| TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
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--RegionEnd;
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// Count the boundary instruction.
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--RemainingCount;
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}
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// The next region starts above the previous region. Look backward in the
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// instruction stream until we find the nearest boundary.
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MachineBasicBlock::iterator I = RegionEnd;
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for(;I != MBB->begin(); --I, --RemainingCount) {
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if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
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break;
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}
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// Notify the scheduler of the region, even if we may skip scheduling
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// it. Perhaps it still needs to be bundled.
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Scheduler->enterRegion(MBB, I, RegionEnd, RemainingCount);
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// Skip empty scheduling regions (0 or 1 schedulable instructions).
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if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
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// Close the current region. Bundle the terminator if needed.
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// This invalidates 'RegionEnd' and 'I'.
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Scheduler->exitRegion();
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continue;
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}
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(dbgs() << MF->getName()
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<< ":BB#" << MBB->getNumber() << "\n From: " << *I << " To: ";
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if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
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else dbgs() << "End";
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dbgs() << " Remaining: " << RemainingCount << "\n");
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// Schedule a region: possibly reorder instructions.
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// This invalidates 'RegionEnd' and 'I'.
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Scheduler->schedule();
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// Close the current region.
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Scheduler->exitRegion();
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// Scheduling has invalidated the current iterator 'I'. Ask the
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// scheduler for the top of it's scheduled region.
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RegionEnd = Scheduler->begin();
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}
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assert(RemainingCount == 0 && "Instruction count mismatch!");
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Scheduler->finishBlock();
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}
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Scheduler->finalizeSchedule();
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DEBUG(LIS->print(dbgs()));
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return true;
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}
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void MachineScheduler::print(raw_ostream &O, const Module* m) const {
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// unimplemented
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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void ReadyQueue::dump() {
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dbgs() << Name << ": ";
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for (unsigned i = 0, e = Queue.size(); i < e; ++i)
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dbgs() << Queue[i]->NodeNum << " ";
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dbgs() << "\n";
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}
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#endif
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//===----------------------------------------------------------------------===//
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// ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals
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// preservation.
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//===----------------------------------------------------------------------===//
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
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/// NumPredsLeft reaches zero, release the successor node.
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///
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/// FIXME: Adjust SuccSU height based on MinLatency.
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void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
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SUnit *SuccSU = SuccEdge->getSUnit();
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#ifndef NDEBUG
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if (SuccSU->NumPredsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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SuccSU->dump(this);
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dbgs() << " has been released too many times!\n";
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llvm_unreachable(0);
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}
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#endif
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--SuccSU->NumPredsLeft;
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if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
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SchedImpl->releaseTopNode(SuccSU);
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}
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/// releaseSuccessors - Call releaseSucc on each of SU's successors.
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void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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releaseSucc(SU, &*I);
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}
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}
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
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/// NumSuccsLeft reaches zero, release the predecessor node.
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///
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/// FIXME: Adjust PredSU height based on MinLatency.
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void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
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SUnit *PredSU = PredEdge->getSUnit();
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#ifndef NDEBUG
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if (PredSU->NumSuccsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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PredSU->dump(this);
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dbgs() << " has been released too many times!\n";
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llvm_unreachable(0);
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}
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#endif
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--PredSU->NumSuccsLeft;
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if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
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SchedImpl->releaseBottomNode(PredSU);
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}
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/// releasePredecessors - Call releasePred on each of SU's predecessors.
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void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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releasePred(SU, &*I);
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}
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}
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void ScheduleDAGMI::moveInstruction(MachineInstr *MI,
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MachineBasicBlock::iterator InsertPos) {
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// Advance RegionBegin if the first instruction moves down.
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if (&*RegionBegin == MI)
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++RegionBegin;
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// Update the instruction stream.
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BB->splice(InsertPos, BB, MI);
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// Update LiveIntervals
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LIS->handleMove(MI);
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// Recede RegionBegin if an instruction moves above the first.
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if (RegionBegin == InsertPos)
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RegionBegin = MI;
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}
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bool ScheduleDAGMI::checkSchedLimit() {
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#ifndef NDEBUG
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if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
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CurrentTop = CurrentBottom;
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return false;
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}
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++NumInstrsScheduled;
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#endif
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return true;
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}
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/// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
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/// crossing a scheduling boundary. [begin, end) includes all instructions in
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/// the region, including the boundary itself and single-instruction regions
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/// that don't get scheduled.
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void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned endcount)
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{
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ScheduleDAGInstrs::enterRegion(bb, begin, end, endcount);
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// For convenience remember the end of the liveness region.
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LiveRegionEnd =
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(RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd);
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}
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// Setup the register pressure trackers for the top scheduled top and bottom
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// scheduled regions.
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void ScheduleDAGMI::initRegPressure() {
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TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
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BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
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// Close the RPTracker to finalize live ins.
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RPTracker.closeRegion();
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DEBUG(RPTracker.getPressure().dump(TRI));
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// Initialize the live ins and live outs.
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TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
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BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
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// Close one end of the tracker so we can call
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// getMaxUpward/DownwardPressureDelta before advancing across any
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// instructions. This converts currently live regs into live ins/outs.
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TopRPTracker.closeTop();
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BotRPTracker.closeBottom();
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// Account for liveness generated by the region boundary.
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if (LiveRegionEnd != RegionEnd)
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BotRPTracker.recede();
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assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
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// Cache the list of excess pressure sets in this region. This will also track
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// the max pressure in the scheduled code for these sets.
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RegionCriticalPSets.clear();
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std::vector<unsigned> RegionPressure = RPTracker.getPressure().MaxSetPressure;
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for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
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unsigned Limit = TRI->getRegPressureSetLimit(i);
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DEBUG(dbgs() << TRI->getRegPressureSetName(i)
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<< "Limit " << Limit
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<< " Actual " << RegionPressure[i] << "\n");
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if (RegionPressure[i] > Limit)
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RegionCriticalPSets.push_back(PressureElement(i, 0));
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}
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DEBUG(dbgs() << "Excess PSets: ";
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for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
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dbgs() << TRI->getRegPressureSetName(
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RegionCriticalPSets[i].PSetID) << " ";
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dbgs() << "\n");
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}
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// FIXME: When the pressure tracker deals in pressure differences then we won't
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// iterate over all RegionCriticalPSets[i].
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void ScheduleDAGMI::
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updateScheduledPressure(std::vector<unsigned> NewMaxPressure) {
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for (unsigned i = 0, e = RegionCriticalPSets.size(); i < e; ++i) {
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unsigned ID = RegionCriticalPSets[i].PSetID;
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int &MaxUnits = RegionCriticalPSets[i].UnitIncrease;
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if ((int)NewMaxPressure[ID] > MaxUnits)
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MaxUnits = NewMaxPressure[ID];
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}
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}
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// Release all DAG roots for scheduling.
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void ScheduleDAGMI::releaseRoots() {
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SmallVector<SUnit*, 16> BotRoots;
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for (std::vector<SUnit>::iterator
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I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
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// A SUnit is ready to top schedule if it has no predecessors.
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if (I->Preds.empty())
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SchedImpl->releaseTopNode(&(*I));
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// A SUnit is ready to bottom schedule if it has no successors.
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if (I->Succs.empty())
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BotRoots.push_back(&(*I));
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}
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// Release bottom roots in reverse order so the higher priority nodes appear
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// first. This is more natural and slightly more efficient.
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for (SmallVectorImpl<SUnit*>::const_reverse_iterator
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I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I)
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SchedImpl->releaseBottomNode(*I);
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}
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/// schedule - Called back from MachineScheduler::runOnMachineFunction
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/// after setting up the current scheduling region. [RegionBegin, RegionEnd)
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/// only includes instructions that have DAG nodes, not scheduling boundaries.
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///
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/// This is a skeletal driver, with all the functionality pushed into helpers,
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/// so that it can be easilly extended by experimental schedulers. Generally,
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/// implementing MachineSchedStrategy should be sufficient to implement a new
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/// scheduling algorithm. However, if a scheduler further subclasses
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/// ScheduleDAGMI then it will want to override this virtual method in order to
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/// update any specialized state.
|
|
void ScheduleDAGMI::schedule() {
|
|
buildDAGWithRegPressure();
|
|
|
|
postprocessDAG();
|
|
|
|
DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
|
|
SUnits[su].dumpAll(this));
|
|
|
|
if (ViewMISchedDAGs) viewGraph();
|
|
|
|
initQueues();
|
|
|
|
bool IsTopNode = false;
|
|
while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
|
|
assert(!SU->isScheduled && "Node already scheduled");
|
|
if (!checkSchedLimit())
|
|
break;
|
|
|
|
scheduleMI(SU, IsTopNode);
|
|
|
|
updateQueues(SU, IsTopNode);
|
|
}
|
|
assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
|
|
|
|
placeDebugValues();
|
|
}
|
|
|
|
/// Build the DAG and setup three register pressure trackers.
|
|
void ScheduleDAGMI::buildDAGWithRegPressure() {
|
|
// Initialize the register pressure tracker used by buildSchedGraph.
|
|
RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
|
|
|
|
// Account for liveness generate by the region boundary.
|
|
if (LiveRegionEnd != RegionEnd)
|
|
RPTracker.recede();
|
|
|
|
// Build the DAG, and compute current register pressure.
|
|
buildSchedGraph(AA, &RPTracker);
|
|
if (ViewMISchedDAGs) viewGraph();
|
|
|
|
// Initialize top/bottom trackers after computing region pressure.
|
|
initRegPressure();
|
|
}
|
|
|
|
/// Apply each ScheduleDAGMutation step in order.
|
|
void ScheduleDAGMI::postprocessDAG() {
|
|
for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
|
|
Mutations[i]->apply(this);
|
|
}
|
|
}
|
|
|
|
/// Identify DAG roots and setup scheduler queues.
|
|
void ScheduleDAGMI::initQueues() {
|
|
// Initialize the strategy before modifying the DAG.
|
|
SchedImpl->initialize(this);
|
|
|
|
// Release edges from the special Entry node or to the special Exit node.
|
|
releaseSuccessors(&EntrySU);
|
|
releasePredecessors(&ExitSU);
|
|
|
|
// Release all DAG roots for scheduling.
|
|
releaseRoots();
|
|
|
|
CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
|
|
CurrentBottom = RegionEnd;
|
|
}
|
|
|
|
/// Move an instruction and update register pressure.
|
|
void ScheduleDAGMI::scheduleMI(SUnit *SU, bool IsTopNode) {
|
|
// Move the instruction to its new location in the instruction stream.
|
|
MachineInstr *MI = SU->getInstr();
|
|
|
|
if (IsTopNode) {
|
|
assert(SU->isTopReady() && "node still has unscheduled dependencies");
|
|
if (&*CurrentTop == MI)
|
|
CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
|
|
else {
|
|
moveInstruction(MI, CurrentTop);
|
|
TopRPTracker.setPos(MI);
|
|
}
|
|
|
|
// Update top scheduled pressure.
|
|
TopRPTracker.advance();
|
|
assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
|
|
updateScheduledPressure(TopRPTracker.getPressure().MaxSetPressure);
|
|
}
|
|
else {
|
|
assert(SU->isBottomReady() && "node still has unscheduled dependencies");
|
|
MachineBasicBlock::iterator priorII =
|
|
priorNonDebug(CurrentBottom, CurrentTop);
|
|
if (&*priorII == MI)
|
|
CurrentBottom = priorII;
|
|
else {
|
|
if (&*CurrentTop == MI) {
|
|
CurrentTop = nextIfDebug(++CurrentTop, priorII);
|
|
TopRPTracker.setPos(CurrentTop);
|
|
}
|
|
moveInstruction(MI, CurrentBottom);
|
|
CurrentBottom = MI;
|
|
}
|
|
// Update bottom scheduled pressure.
|
|
BotRPTracker.recede();
|
|
assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
|
|
updateScheduledPressure(BotRPTracker.getPressure().MaxSetPressure);
|
|
}
|
|
}
|
|
|
|
/// Update scheduler queues after scheduling an instruction.
|
|
void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
|
|
// Release dependent instructions for scheduling.
|
|
if (IsTopNode)
|
|
releaseSuccessors(SU);
|
|
else
|
|
releasePredecessors(SU);
|
|
|
|
SU->isScheduled = true;
|
|
|
|
// Notify the scheduling strategy after updating the DAG.
|
|
SchedImpl->schedNode(SU, IsTopNode);
|
|
}
|
|
|
|
/// Reinsert any remaining debug_values, just like the PostRA scheduler.
|
|
void ScheduleDAGMI::placeDebugValues() {
|
|
// If first instruction was a DBG_VALUE then put it back.
|
|
if (FirstDbgValue) {
|
|
BB->splice(RegionBegin, BB, FirstDbgValue);
|
|
RegionBegin = FirstDbgValue;
|
|
}
|
|
|
|
for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
|
|
DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
|
|
std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
|
|
MachineInstr *DbgValue = P.first;
|
|
MachineBasicBlock::iterator OrigPrevMI = P.second;
|
|
BB->splice(++OrigPrevMI, BB, DbgValue);
|
|
if (OrigPrevMI == llvm::prior(RegionEnd))
|
|
RegionEnd = DbgValue;
|
|
}
|
|
DbgValues.clear();
|
|
FirstDbgValue = NULL;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// ConvergingScheduler - Implementation of the standard MachineSchedStrategy.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
namespace {
|
|
/// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance
|
|
/// the schedule.
|
|
class ConvergingScheduler : public MachineSchedStrategy {
|
|
|
|
/// Store the state used by ConvergingScheduler heuristics, required for the
|
|
/// lifetime of one invocation of pickNode().
|
|
struct SchedCandidate {
|
|
// The best SUnit candidate.
|
|
SUnit *SU;
|
|
|
|
// Register pressure values for the best candidate.
|
|
RegPressureDelta RPDelta;
|
|
|
|
SchedCandidate(): SU(NULL) {}
|
|
};
|
|
/// Represent the type of SchedCandidate found within a single queue.
|
|
enum CandResult {
|
|
NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure };
|
|
|
|
/// Each Scheduling boundary is associated with ready queues. It tracks the
|
|
/// current cycle in whichever direction at has moved, and maintains the state
|
|
/// of "hazards" and other interlocks at the current cycle.
|
|
struct SchedBoundary {
|
|
ScheduleDAGMI *DAG;
|
|
|
|
ReadyQueue Available;
|
|
ReadyQueue Pending;
|
|
bool CheckPending;
|
|
|
|
ScheduleHazardRecognizer *HazardRec;
|
|
|
|
unsigned CurrCycle;
|
|
unsigned IssueCount;
|
|
|
|
/// MinReadyCycle - Cycle of the soonest available instruction.
|
|
unsigned MinReadyCycle;
|
|
|
|
// Remember the greatest min operand latency.
|
|
unsigned MaxMinLatency;
|
|
|
|
/// Pending queues extend the ready queues with the same ID and the
|
|
/// PendingFlag set.
|
|
SchedBoundary(unsigned ID, const Twine &Name):
|
|
DAG(0), Available(ID, Name+".A"),
|
|
Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"),
|
|
CheckPending(false), HazardRec(0), CurrCycle(0), IssueCount(0),
|
|
MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
|
|
|
|
~SchedBoundary() { delete HazardRec; }
|
|
|
|
bool isTop() const {
|
|
return Available.getID() == ConvergingScheduler::TopQID;
|
|
}
|
|
|
|
bool checkHazard(SUnit *SU);
|
|
|
|
void releaseNode(SUnit *SU, unsigned ReadyCycle);
|
|
|
|
void bumpCycle();
|
|
|
|
void bumpNode(SUnit *SU);
|
|
|
|
void releasePending();
|
|
|
|
void removeReady(SUnit *SU);
|
|
|
|
SUnit *pickOnlyChoice();
|
|
};
|
|
|
|
ScheduleDAGMI *DAG;
|
|
const TargetRegisterInfo *TRI;
|
|
|
|
// State of the top and bottom scheduled instruction boundaries.
|
|
SchedBoundary Top;
|
|
SchedBoundary Bot;
|
|
|
|
public:
|
|
/// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
|
|
enum {
|
|
TopQID = 1,
|
|
BotQID = 2,
|
|
LogMaxQID = 2
|
|
};
|
|
|
|
ConvergingScheduler():
|
|
DAG(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
|
|
|
|
virtual void initialize(ScheduleDAGMI *dag);
|
|
|
|
virtual SUnit *pickNode(bool &IsTopNode);
|
|
|
|
virtual void schedNode(SUnit *SU, bool IsTopNode);
|
|
|
|
virtual void releaseTopNode(SUnit *SU);
|
|
|
|
virtual void releaseBottomNode(SUnit *SU);
|
|
|
|
protected:
|
|
SUnit *pickNodeBidrectional(bool &IsTopNode);
|
|
|
|
CandResult pickNodeFromQueue(ReadyQueue &Q,
|
|
const RegPressureTracker &RPTracker,
|
|
SchedCandidate &Candidate);
|
|
#ifndef NDEBUG
|
|
void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
|
|
PressureElement P = PressureElement());
|
|
#endif
|
|
};
|
|
} // namespace
|
|
|
|
void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
|
|
DAG = dag;
|
|
TRI = DAG->TRI;
|
|
Top.DAG = dag;
|
|
Bot.DAG = dag;
|
|
|
|
// Initialize the HazardRecognizers.
|
|
const TargetMachine &TM = DAG->MF.getTarget();
|
|
const InstrItineraryData *Itin = TM.getInstrItineraryData();
|
|
Top.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
|
|
Bot.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
|
|
|
|
assert((!ForceTopDown || !ForceBottomUp) &&
|
|
"-misched-topdown incompatible with -misched-bottomup");
|
|
}
|
|
|
|
void ConvergingScheduler::releaseTopNode(SUnit *SU) {
|
|
if (SU->isScheduled)
|
|
return;
|
|
|
|
for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
|
|
unsigned MinLatency = I->getMinLatency();
|
|
#ifndef NDEBUG
|
|
Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency);
|
|
#endif
|
|
if (SU->TopReadyCycle < PredReadyCycle + MinLatency)
|
|
SU->TopReadyCycle = PredReadyCycle + MinLatency;
|
|
}
|
|
Top.releaseNode(SU, SU->TopReadyCycle);
|
|
}
|
|
|
|
void ConvergingScheduler::releaseBottomNode(SUnit *SU) {
|
|
if (SU->isScheduled)
|
|
return;
|
|
|
|
assert(SU->getInstr() && "Scheduled SUnit must have instr");
|
|
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
|
|
unsigned MinLatency = I->getMinLatency();
|
|
#ifndef NDEBUG
|
|
Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency);
|
|
#endif
|
|
if (SU->BotReadyCycle < SuccReadyCycle + MinLatency)
|
|
SU->BotReadyCycle = SuccReadyCycle + MinLatency;
|
|
}
|
|
Bot.releaseNode(SU, SU->BotReadyCycle);
|
|
}
|
|
|
|
/// Does this SU have a hazard within the current instruction group.
|
|
///
|
|
/// The scheduler supports two modes of hazard recognition. The first is the
|
|
/// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
|
|
/// supports highly complicated in-order reservation tables
|
|
/// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
|
|
///
|
|
/// The second is a streamlined mechanism that checks for hazards based on
|
|
/// simple counters that the scheduler itself maintains. It explicitly checks
|
|
/// for instruction dispatch limitations, including the number of micro-ops that
|
|
/// can dispatch per cycle.
|
|
///
|
|
/// TODO: Also check whether the SU must start a new group.
|
|
bool ConvergingScheduler::SchedBoundary::checkHazard(SUnit *SU) {
|
|
if (HazardRec->isEnabled())
|
|
return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
|
|
|
|
if (IssueCount + DAG->getNumMicroOps(SU->getInstr()) > DAG->getIssueWidth())
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
void ConvergingScheduler::SchedBoundary::releaseNode(SUnit *SU,
|
|
unsigned ReadyCycle) {
|
|
if (ReadyCycle < MinReadyCycle)
|
|
MinReadyCycle = ReadyCycle;
|
|
|
|
// Check for interlocks first. For the purpose of other heuristics, an
|
|
// instruction that cannot issue appears as if it's not in the ReadyQueue.
|
|
if (ReadyCycle > CurrCycle || checkHazard(SU))
|
|
Pending.push(SU);
|
|
else
|
|
Available.push(SU);
|
|
}
|
|
|
|
/// Move the boundary of scheduled code by one cycle.
|
|
void ConvergingScheduler::SchedBoundary::bumpCycle() {
|
|
unsigned Width = DAG->getIssueWidth();
|
|
IssueCount = (IssueCount <= Width) ? 0 : IssueCount - Width;
|
|
|
|
assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
|
|
unsigned NextCycle = std::max(CurrCycle + 1, MinReadyCycle);
|
|
|
|
if (!HazardRec->isEnabled()) {
|
|
// Bypass HazardRec virtual calls.
|
|
CurrCycle = NextCycle;
|
|
}
|
|
else {
|
|
// Bypass getHazardType calls in case of long latency.
|
|
for (; CurrCycle != NextCycle; ++CurrCycle) {
|
|
if (isTop())
|
|
HazardRec->AdvanceCycle();
|
|
else
|
|
HazardRec->RecedeCycle();
|
|
}
|
|
}
|
|
CheckPending = true;
|
|
|
|
DEBUG(dbgs() << "*** " << Available.getName() << " cycle "
|
|
<< CurrCycle << '\n');
|
|
}
|
|
|
|
/// Move the boundary of scheduled code by one SUnit.
|
|
void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU) {
|
|
// Update the reservation table.
|
|
if (HazardRec->isEnabled()) {
|
|
if (!isTop() && SU->isCall) {
|
|
// Calls are scheduled with their preceding instructions. For bottom-up
|
|
// scheduling, clear the pipeline state before emitting.
|
|
HazardRec->Reset();
|
|
}
|
|
HazardRec->EmitInstruction(SU);
|
|
}
|
|
// Check the instruction group dispatch limit.
|
|
// TODO: Check if this SU must end a dispatch group.
|
|
IssueCount += DAG->getNumMicroOps(SU->getInstr());
|
|
if (IssueCount >= DAG->getIssueWidth()) {
|
|
DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n');
|
|
bumpCycle();
|
|
}
|
|
}
|
|
|
|
/// Release pending ready nodes in to the available queue. This makes them
|
|
/// visible to heuristics.
|
|
void ConvergingScheduler::SchedBoundary::releasePending() {
|
|
// If the available queue is empty, it is safe to reset MinReadyCycle.
|
|
if (Available.empty())
|
|
MinReadyCycle = UINT_MAX;
|
|
|
|
// Check to see if any of the pending instructions are ready to issue. If
|
|
// so, add them to the available queue.
|
|
for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
|
|
SUnit *SU = *(Pending.begin()+i);
|
|
unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
|
|
|
|
if (ReadyCycle < MinReadyCycle)
|
|
MinReadyCycle = ReadyCycle;
|
|
|
|
if (ReadyCycle > CurrCycle)
|
|
continue;
|
|
|
|
if (checkHazard(SU))
|
|
continue;
|
|
|
|
Available.push(SU);
|
|
Pending.remove(Pending.begin()+i);
|
|
--i; --e;
|
|
}
|
|
CheckPending = false;
|
|
}
|
|
|
|
/// Remove SU from the ready set for this boundary.
|
|
void ConvergingScheduler::SchedBoundary::removeReady(SUnit *SU) {
|
|
if (Available.isInQueue(SU))
|
|
Available.remove(Available.find(SU));
|
|
else {
|
|
assert(Pending.isInQueue(SU) && "bad ready count");
|
|
Pending.remove(Pending.find(SU));
|
|
}
|
|
}
|
|
|
|
/// If this queue only has one ready candidate, return it. As a side effect,
|
|
/// advance the cycle until at least one node is ready. If multiple instructions
|
|
/// are ready, return NULL.
|
|
SUnit *ConvergingScheduler::SchedBoundary::pickOnlyChoice() {
|
|
if (CheckPending)
|
|
releasePending();
|
|
|
|
for (unsigned i = 0; Available.empty(); ++i) {
|
|
assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) &&
|
|
"permanent hazard"); (void)i;
|
|
bumpCycle();
|
|
releasePending();
|
|
}
|
|
if (Available.size() == 1)
|
|
return *Available.begin();
|
|
return NULL;
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
void ConvergingScheduler::traceCandidate(const char *Label, const ReadyQueue &Q,
|
|
SUnit *SU, PressureElement P) {
|
|
dbgs() << Label << " " << Q.getName() << " ";
|
|
if (P.isValid())
|
|
dbgs() << TRI->getRegPressureSetName(P.PSetID) << ":" << P.UnitIncrease
|
|
<< " ";
|
|
else
|
|
dbgs() << " ";
|
|
SU->dump(DAG);
|
|
}
|
|
#endif
|
|
|
|
/// pickNodeFromQueue helper that returns true if the LHS reg pressure effect is
|
|
/// more desirable than RHS from scheduling standpoint.
|
|
static bool compareRPDelta(const RegPressureDelta &LHS,
|
|
const RegPressureDelta &RHS) {
|
|
// Compare each component of pressure in decreasing order of importance
|
|
// without checking if any are valid. Invalid PressureElements are assumed to
|
|
// have UnitIncrease==0, so are neutral.
|
|
|
|
// Avoid increasing the max critical pressure in the scheduled region.
|
|
if (LHS.Excess.UnitIncrease != RHS.Excess.UnitIncrease)
|
|
return LHS.Excess.UnitIncrease < RHS.Excess.UnitIncrease;
|
|
|
|
// Avoid increasing the max critical pressure in the scheduled region.
|
|
if (LHS.CriticalMax.UnitIncrease != RHS.CriticalMax.UnitIncrease)
|
|
return LHS.CriticalMax.UnitIncrease < RHS.CriticalMax.UnitIncrease;
|
|
|
|
// Avoid increasing the max pressure of the entire region.
|
|
if (LHS.CurrentMax.UnitIncrease != RHS.CurrentMax.UnitIncrease)
|
|
return LHS.CurrentMax.UnitIncrease < RHS.CurrentMax.UnitIncrease;
|
|
|
|
return false;
|
|
}
|
|
|
|
/// Pick the best candidate from the top queue.
|
|
///
|
|
/// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
|
|
/// DAG building. To adjust for the current scheduling location we need to
|
|
/// maintain the number of vreg uses remaining to be top-scheduled.
|
|
ConvergingScheduler::CandResult ConvergingScheduler::
|
|
pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker,
|
|
SchedCandidate &Candidate) {
|
|
DEBUG(Q.dump());
|
|
|
|
// getMaxPressureDelta temporarily modifies the tracker.
|
|
RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
|
|
|
|
// BestSU remains NULL if no top candidates beat the best existing candidate.
|
|
CandResult FoundCandidate = NoCand;
|
|
for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
|
|
RegPressureDelta RPDelta;
|
|
TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta,
|
|
DAG->getRegionCriticalPSets(),
|
|
DAG->getRegPressure().MaxSetPressure);
|
|
|
|
// Initialize the candidate if needed.
|
|
if (!Candidate.SU) {
|
|
Candidate.SU = *I;
|
|
Candidate.RPDelta = RPDelta;
|
|
FoundCandidate = NodeOrder;
|
|
continue;
|
|
}
|
|
// Avoid exceeding the target's limit.
|
|
if (RPDelta.Excess.UnitIncrease < Candidate.RPDelta.Excess.UnitIncrease) {
|
|
DEBUG(traceCandidate("ECAND", Q, *I, RPDelta.Excess));
|
|
Candidate.SU = *I;
|
|
Candidate.RPDelta = RPDelta;
|
|
FoundCandidate = SingleExcess;
|
|
continue;
|
|
}
|
|
if (RPDelta.Excess.UnitIncrease > Candidate.RPDelta.Excess.UnitIncrease)
|
|
continue;
|
|
if (FoundCandidate == SingleExcess)
|
|
FoundCandidate = MultiPressure;
|
|
|
|
// Avoid increasing the max critical pressure in the scheduled region.
|
|
if (RPDelta.CriticalMax.UnitIncrease
|
|
< Candidate.RPDelta.CriticalMax.UnitIncrease) {
|
|
DEBUG(traceCandidate("PCAND", Q, *I, RPDelta.CriticalMax));
|
|
Candidate.SU = *I;
|
|
Candidate.RPDelta = RPDelta;
|
|
FoundCandidate = SingleCritical;
|
|
continue;
|
|
}
|
|
if (RPDelta.CriticalMax.UnitIncrease
|
|
> Candidate.RPDelta.CriticalMax.UnitIncrease)
|
|
continue;
|
|
if (FoundCandidate == SingleCritical)
|
|
FoundCandidate = MultiPressure;
|
|
|
|
// Avoid increasing the max pressure of the entire region.
|
|
if (RPDelta.CurrentMax.UnitIncrease
|
|
< Candidate.RPDelta.CurrentMax.UnitIncrease) {
|
|
DEBUG(traceCandidate("MCAND", Q, *I, RPDelta.CurrentMax));
|
|
Candidate.SU = *I;
|
|
Candidate.RPDelta = RPDelta;
|
|
FoundCandidate = SingleMax;
|
|
continue;
|
|
}
|
|
if (RPDelta.CurrentMax.UnitIncrease
|
|
> Candidate.RPDelta.CurrentMax.UnitIncrease)
|
|
continue;
|
|
if (FoundCandidate == SingleMax)
|
|
FoundCandidate = MultiPressure;
|
|
|
|
// Fall through to original instruction order.
|
|
// Only consider node order if Candidate was chosen from this Q.
|
|
if (FoundCandidate == NoCand)
|
|
continue;
|
|
|
|
if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum)
|
|
|| (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) {
|
|
DEBUG(traceCandidate("NCAND", Q, *I));
|
|
Candidate.SU = *I;
|
|
Candidate.RPDelta = RPDelta;
|
|
FoundCandidate = NodeOrder;
|
|
}
|
|
}
|
|
return FoundCandidate;
|
|
}
|
|
|
|
/// Pick the best candidate node from either the top or bottom queue.
|
|
SUnit *ConvergingScheduler::pickNodeBidrectional(bool &IsTopNode) {
|
|
// Schedule as far as possible in the direction of no choice. This is most
|
|
// efficient, but also provides the best heuristics for CriticalPSets.
|
|
if (SUnit *SU = Bot.pickOnlyChoice()) {
|
|
IsTopNode = false;
|
|
return SU;
|
|
}
|
|
if (SUnit *SU = Top.pickOnlyChoice()) {
|
|
IsTopNode = true;
|
|
return SU;
|
|
}
|
|
SchedCandidate BotCand;
|
|
// Prefer bottom scheduling when heuristics are silent.
|
|
CandResult BotResult = pickNodeFromQueue(Bot.Available,
|
|
DAG->getBotRPTracker(), BotCand);
|
|
assert(BotResult != NoCand && "failed to find the first candidate");
|
|
|
|
// If either Q has a single candidate that provides the least increase in
|
|
// Excess pressure, we can immediately schedule from that Q.
|
|
//
|
|
// RegionCriticalPSets summarizes the pressure within the scheduled region and
|
|
// affects picking from either Q. If scheduling in one direction must
|
|
// increase pressure for one of the excess PSets, then schedule in that
|
|
// direction first to provide more freedom in the other direction.
|
|
if (BotResult == SingleExcess || BotResult == SingleCritical) {
|
|
IsTopNode = false;
|
|
return BotCand.SU;
|
|
}
|
|
// Check if the top Q has a better candidate.
|
|
SchedCandidate TopCand;
|
|
CandResult TopResult = pickNodeFromQueue(Top.Available,
|
|
DAG->getTopRPTracker(), TopCand);
|
|
assert(TopResult != NoCand && "failed to find the first candidate");
|
|
|
|
if (TopResult == SingleExcess || TopResult == SingleCritical) {
|
|
IsTopNode = true;
|
|
return TopCand.SU;
|
|
}
|
|
// If either Q has a single candidate that minimizes pressure above the
|
|
// original region's pressure pick it.
|
|
if (BotResult == SingleMax) {
|
|
IsTopNode = false;
|
|
return BotCand.SU;
|
|
}
|
|
if (TopResult == SingleMax) {
|
|
IsTopNode = true;
|
|
return TopCand.SU;
|
|
}
|
|
// Check for a salient pressure difference and pick the best from either side.
|
|
if (compareRPDelta(TopCand.RPDelta, BotCand.RPDelta)) {
|
|
IsTopNode = true;
|
|
return TopCand.SU;
|
|
}
|
|
// Otherwise prefer the bottom candidate in node order.
|
|
IsTopNode = false;
|
|
return BotCand.SU;
|
|
}
|
|
|
|
/// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
|
|
SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
|
|
if (DAG->top() == DAG->bottom()) {
|
|
assert(Top.Available.empty() && Top.Pending.empty() &&
|
|
Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
|
|
return NULL;
|
|
}
|
|
SUnit *SU;
|
|
do {
|
|
if (ForceTopDown) {
|
|
SU = Top.pickOnlyChoice();
|
|
if (!SU) {
|
|
SchedCandidate TopCand;
|
|
CandResult TopResult =
|
|
pickNodeFromQueue(Top.Available, DAG->getTopRPTracker(), TopCand);
|
|
assert(TopResult != NoCand && "failed to find the first candidate");
|
|
(void)TopResult;
|
|
SU = TopCand.SU;
|
|
}
|
|
IsTopNode = true;
|
|
}
|
|
else if (ForceBottomUp) {
|
|
SU = Bot.pickOnlyChoice();
|
|
if (!SU) {
|
|
SchedCandidate BotCand;
|
|
CandResult BotResult =
|
|
pickNodeFromQueue(Bot.Available, DAG->getBotRPTracker(), BotCand);
|
|
assert(BotResult != NoCand && "failed to find the first candidate");
|
|
(void)BotResult;
|
|
SU = BotCand.SU;
|
|
}
|
|
IsTopNode = false;
|
|
}
|
|
else {
|
|
SU = pickNodeBidrectional(IsTopNode);
|
|
}
|
|
} while (SU->isScheduled);
|
|
|
|
if (SU->isTopReady())
|
|
Top.removeReady(SU);
|
|
if (SU->isBottomReady())
|
|
Bot.removeReady(SU);
|
|
|
|
DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom")
|
|
<< " Scheduling Instruction in cycle "
|
|
<< (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << '\n';
|
|
SU->dump(DAG));
|
|
return SU;
|
|
}
|
|
|
|
/// Update the scheduler's state after scheduling a node. This is the same node
|
|
/// that was just returned by pickNode(). However, ScheduleDAGMI needs to update
|
|
/// it's state based on the current cycle before MachineSchedStrategy does.
|
|
void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
|
|
if (IsTopNode) {
|
|
SU->TopReadyCycle = Top.CurrCycle;
|
|
Top.bumpNode(SU);
|
|
}
|
|
else {
|
|
SU->BotReadyCycle = Bot.CurrCycle;
|
|
Bot.bumpNode(SU);
|
|
}
|
|
}
|
|
|
|
/// Create the standard converging machine scheduler. This will be used as the
|
|
/// default scheduler if the target does not set a default.
|
|
static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
|
|
assert((!ForceTopDown || !ForceBottomUp) &&
|
|
"-misched-topdown incompatible with -misched-bottomup");
|
|
return new ScheduleDAGMI(C, new ConvergingScheduler());
|
|
}
|
|
static MachineSchedRegistry
|
|
ConvergingSchedRegistry("converge", "Standard converging scheduler.",
|
|
createConvergingSched);
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Machine Instruction Shuffler for Correctness Testing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef NDEBUG
|
|
namespace {
|
|
/// Apply a less-than relation on the node order, which corresponds to the
|
|
/// instruction order prior to scheduling. IsReverse implements greater-than.
|
|
template<bool IsReverse>
|
|
struct SUnitOrder {
|
|
bool operator()(SUnit *A, SUnit *B) const {
|
|
if (IsReverse)
|
|
return A->NodeNum > B->NodeNum;
|
|
else
|
|
return A->NodeNum < B->NodeNum;
|
|
}
|
|
};
|
|
|
|
/// Reorder instructions as much as possible.
|
|
class InstructionShuffler : public MachineSchedStrategy {
|
|
bool IsAlternating;
|
|
bool IsTopDown;
|
|
|
|
// Using a less-than relation (SUnitOrder<false>) for the TopQ priority
|
|
// gives nodes with a higher number higher priority causing the latest
|
|
// instructions to be scheduled first.
|
|
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
|
|
TopQ;
|
|
// When scheduling bottom-up, use greater-than as the queue priority.
|
|
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
|
|
BottomQ;
|
|
public:
|
|
InstructionShuffler(bool alternate, bool topdown)
|
|
: IsAlternating(alternate), IsTopDown(topdown) {}
|
|
|
|
virtual void initialize(ScheduleDAGMI *) {
|
|
TopQ.clear();
|
|
BottomQ.clear();
|
|
}
|
|
|
|
/// Implement MachineSchedStrategy interface.
|
|
/// -----------------------------------------
|
|
|
|
virtual SUnit *pickNode(bool &IsTopNode) {
|
|
SUnit *SU;
|
|
if (IsTopDown) {
|
|
do {
|
|
if (TopQ.empty()) return NULL;
|
|
SU = TopQ.top();
|
|
TopQ.pop();
|
|
} while (SU->isScheduled);
|
|
IsTopNode = true;
|
|
}
|
|
else {
|
|
do {
|
|
if (BottomQ.empty()) return NULL;
|
|
SU = BottomQ.top();
|
|
BottomQ.pop();
|
|
} while (SU->isScheduled);
|
|
IsTopNode = false;
|
|
}
|
|
if (IsAlternating)
|
|
IsTopDown = !IsTopDown;
|
|
return SU;
|
|
}
|
|
|
|
virtual void schedNode(SUnit *SU, bool IsTopNode) {}
|
|
|
|
virtual void releaseTopNode(SUnit *SU) {
|
|
TopQ.push(SU);
|
|
}
|
|
virtual void releaseBottomNode(SUnit *SU) {
|
|
BottomQ.push(SU);
|
|
}
|
|
};
|
|
} // namespace
|
|
|
|
static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
|
|
bool Alternate = !ForceTopDown && !ForceBottomUp;
|
|
bool TopDown = !ForceBottomUp;
|
|
assert((TopDown || !ForceTopDown) &&
|
|
"-misched-topdown incompatible with -misched-bottomup");
|
|
return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown));
|
|
}
|
|
static MachineSchedRegistry ShufflerRegistry(
|
|
"shuffle", "Shuffle machine instructions alternating directions",
|
|
createInstructionShuffler);
|
|
#endif // !NDEBUG
|