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https://github.com/c64scene-ar/llvm-6502.git
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6dc4d8f0ed
We were passing the scratch buffer address to the shaders via user sgprs, but now we use external symbols and have the driver patch the shader using reloc information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226586 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
4.1 KiB
C++
121 lines
4.1 KiB
C++
//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIRegisterInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
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#define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
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#include "AMDGPURegisterInfo.h"
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namespace llvm {
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struct SIRegisterInfo : public AMDGPURegisterInfo {
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SIRegisterInfo(const AMDGPUSubtarget &st);
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const override;
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/// \brief get the register class of the specified type to use in the
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/// CFGStructurizer
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const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
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unsigned getHWRegIndex(unsigned Reg) const override;
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/// \brief Return the 'base' register class for this register.
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/// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
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const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
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/// \returns true if this class contains only SGPR registers
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bool isSGPRClass(const TargetRegisterClass *RC) const {
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if (!RC)
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return false;
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return !hasVGPRs(RC);
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}
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/// \returns true if this class ID contains only SGPR registers
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bool isSGPRClassID(unsigned RCID) const {
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if (static_cast<int>(RCID) == -1)
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return false;
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return isSGPRClass(getRegClass(RCID));
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}
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/// \returns true if this class contains VGPR registers.
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bool hasVGPRs(const TargetRegisterClass *RC) const;
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/// \returns A VGPR reg class with the same width as \p SRC
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const TargetRegisterClass *getEquivalentVGPRClass(
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const TargetRegisterClass *SRC) const;
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/// \returns The register class that is used for a sub-register of \p RC for
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/// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
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/// be returned.
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const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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unsigned SubIdx) const;
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/// \p Channel This is the register channel (e.g. a value from 0-16), not the
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/// SubReg index.
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/// \returns The sub-register of Reg that is in Channel.
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unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
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unsigned Channel) const;
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/// \returns True if operands defined with this operand type can accept
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/// a literal constant (i.e. any 32-bit immediate).
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bool opCanUseLiteralConstant(unsigned OpType) const;
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/// \returns True if operands defined with this operand type can accept
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/// an inline constant. i.e. An integer value in the range (-16, 64) or
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/// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
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bool opCanUseInlineConstant(unsigned OpType) const;
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enum PreloadedValue {
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TGID_X,
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TGID_Y,
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TGID_Z,
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SCRATCH_WAVE_OFFSET,
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SCRATCH_PTR,
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INPUT_PTR,
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TIDIG_X,
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TIDIG_Y,
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TIDIG_Z
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};
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/// \brief Returns the physical register that \p Value is stored in.
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unsigned getPreloadedValue(const MachineFunction &MF,
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enum PreloadedValue Value) const;
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unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
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const TargetRegisterClass *RC) const;
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private:
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void buildScratchLoadStore(MachineBasicBlock::iterator MI,
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unsigned LoadStoreOp, unsigned Value,
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unsigned ScratchRsrcReg, unsigned ScratchOffset,
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int64_t Offset, RegScavenger *RS) const;
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};
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} // End namespace llvm
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#endif
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