Kit Barton f60b0de42a This change implements the following three logical vector operations: ... veqv (vector equivalence) vnand vorc I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions. Phabricator review: http://reviews.llvm.org/D7469 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228580 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-09 17:03:18 +00:00
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AArch64	Condition codes AL and NV are invalid in the aliases that use	2014-06-10 13:11:35 +00:00
ARM	Add support for ARM modified-immediate assembly syntax.	2014-12-02 10:53:20 +00:00
Hexagon	[Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests.	2015-02-03 19:15:11 +00:00
Mips	[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.	2015-01-29 11:33:41 +00:00
PowerPC	This change implements the following three logical vector operations:	2015-02-09 17:03:18 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	[SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA	2014-07-10 11:00:55 +00:00
X86	[X86] Add GETSEC instruction.	2015-02-07 23:36:36 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00