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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207510 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
4.5 KiB
C++
113 lines
4.5 KiB
C++
//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_AARCH64INSTRINFO_H
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#define LLVM_TARGET_AARCH64INSTRINFO_H
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#include "AArch64RegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "AArch64GenInstrInfo.inc"
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namespace llvm {
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class AArch64Subtarget;
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class AArch64InstrInfo : public AArch64GenInstrInfo {
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const AArch64RegisterInfo RI;
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const AArch64Subtarget &Subtarget;
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public:
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explicit AArch64InstrInfo(const AArch64Subtarget &TM);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const TargetRegisterInfo &getRegisterInfo() const { return RI; }
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const AArch64Subtarget &getSubTarget() const { return Subtarget; }
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void CopyPhysRegTuple(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg) const;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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/// Look through the instructions in this function and work out the largest
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/// the stack frame can be while maintaining the ability to address local
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/// slots with no complexities.
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unsigned estimateRSStackLimit(MachineFunction &MF) const;
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/// getAddressConstraints - For loads and stores (and PRFMs) taking an
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/// immediate offset, this function determines the constraints required for
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/// the immediate. It must satisfy:
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/// + MinOffset <= imm <= MaxOffset
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/// + imm % OffsetScale == 0
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void getAddressConstraints(const MachineInstr &MI, int &AccessScale,
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int &MinOffset, int &MaxOffset) const;
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unsigned getInstSizeInBytes(const MachineInstr &MI) const;
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unsigned getInstBundleLength(const MachineInstr &MI) const;
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};
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bool rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const AArch64InstrInfo &TII);
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void emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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DebugLoc dl, const TargetInstrInfo &TII,
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unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
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int64_t NumBytes,
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MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags);
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void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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DebugLoc dl, const TargetInstrInfo &TII,
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unsigned ScratchReg, int64_t NumBytes,
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MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags);
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}
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#endif
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