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65b74e1d00
instruction introduced in AVX, which can operate on 128 and 256-bit vectors. It considers a 256-bit vector as two independent 128-bit lanes. It can permute any 32 or 64 elements inside a lane, and restricts the second lane to have the same permutation of the first one. With the improved splat support introduced early today, adding codegen for this instruction enable more efficient 256-bit code: Instead of: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vextractf128 $1, %ymm0, %xmm1 shufps $1, %xmm1, %xmm1 movss %xmm1, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm1, 20(%rsp) movss %xmm1, 16(%rsp) vextractf128 $0, %ymm0, %xmm0 shufps $1, %xmm0, %xmm0 movss %xmm0, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm0, (%rsp) vmovaps (%rsp), %ymm0 We get: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vpermilps $85, %ymm0, %ymm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
271 lines
9.0 KiB
C++
271 lines
9.0 KiB
C++
//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This defines functionality used to emit comments about X86 instructions to
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// an output stream for -fverbose-asm.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstComments.h"
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/raw_ostream.h"
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#include "../Utils/X86ShuffleDecode.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Top Level Entrypoint
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//===----------------------------------------------------------------------===//
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/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
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/// newline terminated strings to the specified string if desired. This
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/// information is shown in disassembly dumps when verbose assembly is enabled.
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void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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const char *(*getRegName)(unsigned)) {
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// If this is a shuffle operation, the switch should fill in this state.
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SmallVector<unsigned, 8> ShuffleMask;
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const char *DestName = 0, *Src1Name = 0, *Src2Name = 0;
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switch (MI->getOpcode()) {
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case X86::INSERTPSrr:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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Src2Name = getRegName(MI->getOperand(2).getReg());
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DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
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break;
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case X86::MOVLHPSrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodeMOVLHPSMask(2, ShuffleMask);
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break;
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case X86::MOVHLPSrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodeMOVHLPSMask(2, ShuffleMask);
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break;
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case X86::PSHUFDri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::PSHUFDmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodePSHUFMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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break;
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case X86::PSHUFHWri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::PSHUFHWmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodePSHUFHWMask(MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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break;
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case X86::PSHUFLWri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::PSHUFLWmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodePSHUFLWMask(MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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break;
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case X86::PUNPCKHBWrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PUNPCKHBWrm:
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodePUNPCKHMask(16, ShuffleMask);
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break;
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case X86::PUNPCKHWDrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PUNPCKHWDrm:
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodePUNPCKHMask(8, ShuffleMask);
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break;
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case X86::PUNPCKHDQrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PUNPCKHDQrm:
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodePUNPCKHMask(4, ShuffleMask);
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break;
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case X86::PUNPCKHQDQrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PUNPCKHQDQrm:
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodePUNPCKHMask(2, ShuffleMask);
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break;
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case X86::PUNPCKLBWrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PUNPCKLBWrm:
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodePUNPCKLBWMask(16, ShuffleMask);
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break;
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case X86::PUNPCKLWDrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PUNPCKLWDrm:
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodePUNPCKLWDMask(8, ShuffleMask);
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break;
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case X86::PUNPCKLDQrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PUNPCKLDQrm:
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodePUNPCKLDQMask(4, ShuffleMask);
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break;
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case X86::PUNPCKLQDQrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PUNPCKLQDQrm:
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Src1Name = getRegName(MI->getOperand(0).getReg());
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DecodePUNPCKLQDQMask(2, ShuffleMask);
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break;
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case X86::SHUFPDrri:
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DecodeSHUFPSMask(2, MI->getOperand(3).getImm(), ShuffleMask);
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Src1Name = getRegName(MI->getOperand(0).getReg());
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Src2Name = getRegName(MI->getOperand(2).getReg());
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break;
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case X86::SHUFPSrri:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::SHUFPSrmi:
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DecodeSHUFPSMask(4, MI->getOperand(3).getImm(), ShuffleMask);
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Src1Name = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::UNPCKLPDrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::UNPCKLPDrm:
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DecodeUNPCKLPDMask(2, ShuffleMask);
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Src1Name = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::VUNPCKLPDrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::VUNPCKLPDrm:
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DecodeUNPCKLPDMask(2, ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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break;
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case X86::VUNPCKLPDYrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::VUNPCKLPDYrm:
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DecodeUNPCKLPDMask(4, ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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break;
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case X86::UNPCKLPSrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::UNPCKLPSrm:
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DecodeUNPCKLPSMask(4, ShuffleMask);
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Src1Name = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::VUNPCKLPSrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::VUNPCKLPSrm:
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DecodeUNPCKLPSMask(4, ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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break;
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case X86::VUNPCKLPSYrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::VUNPCKLPSYrm:
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DecodeUNPCKLPSMask(8, ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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break;
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case X86::UNPCKHPDrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::UNPCKHPDrm:
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DecodeUNPCKHPMask(2, ShuffleMask);
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Src1Name = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::UNPCKHPSrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::UNPCKHPSrm:
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DecodeUNPCKHPMask(4, ShuffleMask);
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Src1Name = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::VPERMILPSYri:
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DecodeVPERMILPSMask(8, MI->getOperand(2).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::VPERMILPDYri:
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DecodeVPERMILPSMask(4, MI->getOperand(2).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(0).getReg());
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break;
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}
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// If this was a shuffle operation, print the shuffle mask.
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if (!ShuffleMask.empty()) {
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if (DestName == 0) DestName = Src1Name;
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OS << (DestName ? DestName : "mem") << " = ";
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// If the two sources are the same, canonicalize the input elements to be
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// from the first src so that we get larger element spans.
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if (Src1Name == Src2Name) {
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for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
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if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
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ShuffleMask[i] >= e) // From second mask.
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ShuffleMask[i] -= e;
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}
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}
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// The shuffle mask specifies which elements of the src1/src2 fill in the
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// destination, with a few sentinel values. Loop through and print them
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// out.
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for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
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if (i != 0)
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OS << ',';
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if (ShuffleMask[i] == SM_SentinelZero) {
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OS << "zero";
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continue;
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}
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// Otherwise, it must come from src1 or src2. Print the span of elements
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// that comes from this src.
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bool isSrc1 = ShuffleMask[i] < ShuffleMask.size();
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const char *SrcName = isSrc1 ? Src1Name : Src2Name;
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OS << (SrcName ? SrcName : "mem") << '[';
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bool IsFirst = true;
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while (i != e &&
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(int)ShuffleMask[i] >= 0 &&
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(ShuffleMask[i] < ShuffleMask.size()) == isSrc1) {
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if (!IsFirst)
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OS << ',';
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else
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IsFirst = false;
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OS << ShuffleMask[i] % ShuffleMask.size();
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++i;
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}
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OS << ']';
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--i; // For loop increments element #.
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}
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//MI->print(OS, 0);
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OS << "\n";
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}
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}
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