mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 03:29:22 +00:00
f63be7d395
XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22340 91177308-0d34-0410-b5e6-96231b3b80d8
512 lines
18 KiB
C++
512 lines
18 KiB
C++
//===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the X86 machine instructions into
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// relocatable machine code.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86Relocations.h"
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#include "X86.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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namespace {
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Statistic<>
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NumEmitted("x86-emitter", "Number of machine instructions emitted");
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}
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namespace {
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class Emitter : public MachineFunctionPass {
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const X86InstrInfo *II;
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MachineCodeEmitter &MCE;
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std::map<const MachineBasicBlock*, unsigned> BasicBlockAddrs;
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std::vector<std::pair<const MachineBasicBlock *, unsigned> > BBRefs;
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public:
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explicit Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {}
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Emitter(MachineCodeEmitter &mce, const X86InstrInfo& ii)
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: II(&ii), MCE(mce) {}
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bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "X86 Machine Code Emitter";
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}
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void emitInstruction(const MachineInstr &MI);
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private:
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void emitBasicBlock(const MachineBasicBlock &MBB);
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void emitPCRelativeBlockAddress(const MachineBasicBlock *BB);
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void emitPCRelativeValue(unsigned Address);
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void emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall);
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void emitGlobalAddressForPtr(GlobalValue *GV, int Disp = 0);
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void emitExternalSymbolAddress(const char *ES, bool isPCRelative,
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bool isTailCall);
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void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
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void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
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void emitConstant(unsigned Val, unsigned Size);
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void emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField);
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};
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
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/// machine code emitted. This uses a MachineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool X86TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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MachineCodeEmitter &MCE) {
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PM.add(new Emitter(MCE));
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// Delete machine code for this function
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PM.add(createMachineCodeDeleter());
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return false;
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}
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bool Emitter::runOnMachineFunction(MachineFunction &MF) {
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II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
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MCE.startFunction(MF);
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MCE.emitConstantPool(MF.getConstantPool());
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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emitBasicBlock(*I);
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MCE.finishFunction(MF);
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// Resolve all forward branches now...
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for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
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unsigned Location = BasicBlockAddrs[BBRefs[i].first];
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unsigned Ref = BBRefs[i].second;
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MCE.emitWordAt(Location-Ref-4, (unsigned*)(intptr_t)Ref);
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}
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BBRefs.clear();
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BasicBlockAddrs.clear();
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return false;
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}
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void Emitter::emitBasicBlock(const MachineBasicBlock &MBB) {
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if (uint64_t Addr = MCE.getCurrentPCValue())
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BasicBlockAddrs[&MBB] = Addr;
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for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I)
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emitInstruction(*I);
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}
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/// emitPCRelativeValue - Emit a 32-bit PC relative address.
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///
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void Emitter::emitPCRelativeValue(unsigned Address) {
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MCE.emitWord(Address-MCE.getCurrentPCValue()-4);
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}
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/// emitPCRelativeBlockAddress - This method emits the PC relative address of
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/// the specified basic block, or if the basic block hasn't been emitted yet
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/// (because this is a forward branch), it keeps track of the information
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/// necessary to resolve this address later (and emits a dummy value).
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///
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void Emitter::emitPCRelativeBlockAddress(const MachineBasicBlock *MBB) {
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// If this is a backwards branch, we already know the address of the target,
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// so just emit the value.
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std::map<const MachineBasicBlock*, unsigned>::iterator I =
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BasicBlockAddrs.find(MBB);
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if (I != BasicBlockAddrs.end()) {
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emitPCRelativeValue(I->second);
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} else {
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// Otherwise, remember where this reference was and where it is to so we can
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// deal with it later.
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BBRefs.push_back(std::make_pair(MBB, MCE.getCurrentPCValue()));
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MCE.emitWord(0);
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}
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}
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/// emitGlobalAddressForCall - Emit the specified address to the code stream
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/// assuming this is part of a function call, which is PC relative.
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///
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void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall) {
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MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
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X86::reloc_pcrel_word, GV, 0,
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!isTailCall /*Doesn'tNeedStub*/));
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MCE.emitWord(0);
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}
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/// emitGlobalAddress - Emit the specified address to the code stream assuming
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/// this is part of a "take the address of a global" instruction, which is not
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/// PC relative.
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///
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void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, int Disp /* = 0 */) {
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MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
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X86::reloc_absolute_word, GV));
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MCE.emitWord(Disp); // The relocated value will be added to the displacement
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}
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/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative,
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bool isTailCall) {
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MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
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isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES));
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MCE.emitWord(0);
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}
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/// N86 namespace - Native X86 Register numbers... used by X86 backend.
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///
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namespace N86 {
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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// getX86RegNum - This function maps LLVM register identifiers to their X86
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// specific numbering, which is used in various places encoding instructions.
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//
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static unsigned getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
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case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
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case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
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case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
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case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
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case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
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return RegNo-X86::ST0;
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default:
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assert(MRegisterInfo::isVirtualRegister(RegNo) &&
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"Unknown physical register!");
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assert(0 && "Register allocator hasn't allocated reg correctly yet!");
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return 0;
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}
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}
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
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MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
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}
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void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
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// SIB byte is in the same format as the ModRMByte...
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MCE.emitByte(ModRMByte(SS, Index, Base));
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}
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void Emitter::emitConstant(unsigned Val, unsigned Size) {
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// Output the constant in little endian byte order...
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for (unsigned i = 0; i != Size; ++i) {
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MCE.emitByte(Val & 255);
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Val >>= 8;
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}
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}
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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void Emitter::emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField) {
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const MachineOperand &Op3 = MI.getOperand(Op+3);
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GlobalValue *GV = 0;
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int DispVal = 0;
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if (Op3.isGlobalAddress()) {
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GV = Op3.getGlobal();
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DispVal = Op3.getOffset();
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} else {
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DispVal = Op3.getImmedValue();
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}
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const MachineOperand &Base = MI.getOperand(Op);
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const MachineOperand &Scale = MI.getOperand(Op+1);
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const MachineOperand &IndexReg = MI.getOperand(Op+2);
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unsigned BaseReg = 0;
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if (Base.isConstantPoolIndex()) {
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// Emit a direct address reference [disp32] where the displacement of the
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// constant pool entry is controlled by the MCE.
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assert(!GV && "Constant Pool reference cannot be relative to global!");
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DispVal += MCE.getConstantPoolEntryAddress(Base.getConstantPoolIndex());
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} else {
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BaseReg = Base.getReg();
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}
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// Is a SIB byte needed?
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if (IndexReg.getReg() == 0 && BaseReg != X86::ESP) {
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if (BaseReg == 0) { // Just a displacement?
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// Emit special case [disp32] encoding
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
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if (GV)
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emitGlobalAddressForPtr(GV, DispVal);
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else
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emitConstant(DispVal, 4);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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if (GV) {
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// Emit the most general non-SIB encoding: [REG+disp32]
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MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
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emitGlobalAddressForPtr(GV, DispVal);
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} else if (DispVal == 0 && BaseRegNo != N86::EBP) {
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// Emit simple indirect register encoding... [EAX] f.e.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
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} else if (isDisp8(DispVal)) {
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// Emit the disp8 encoding... [REG+disp8]
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MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(DispVal, 1);
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
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emitConstant(DispVal, 4);
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}
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}
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} else { // We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (GV) {
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// Emit the normal disp32 encoding...
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MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (DispVal == 0 && BaseReg != X86::EBP) {
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// Emit no displacement ModR/M byte
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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} else if (isDisp8(DispVal)) {
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// Emit the disp8 encoding...
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MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else {
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// Emit the normal disp32 encoding...
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MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImmedValue()];
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if (BaseReg == 0) {
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// Handle the SIB byte for the case where there is no base. The
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// displacement has already been output.
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assert(IndexReg.getReg() && "Index register must be specified!");
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emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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else
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IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
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emitSIBByte(SS, IndexRegNo, BaseRegNo);
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}
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// Do we need to output a displacement?
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if (DispVal != 0 || ForceDisp32 || ForceDisp8) {
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if (!ForceDisp32 && isDisp8(DispVal))
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emitConstant(DispVal, 1);
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else if (GV)
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emitGlobalAddressForPtr(GV, DispVal);
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else
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emitConstant(DispVal, 4);
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}
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}
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}
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static unsigned sizeOfImm(const TargetInstrDescriptor &Desc) {
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switch (Desc.TSFlags & X86II::ImmMask) {
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case X86II::Imm8: return 1;
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case X86II::Imm16: return 2;
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case X86II::Imm32: return 4;
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default: assert(0 && "Immediate size not set!");
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return 0;
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}
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}
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void Emitter::emitInstruction(const MachineInstr &MI) {
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NumEmitted++; // Keep track of the # of mi's emitted
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDescriptor &Desc = II->get(Opcode);
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// Emit the repeat opcode prefix as needed.
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if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
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// Emit the operand size opcode prefix as needed.
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
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// Emit the double precision sse fp opcode prefix as needed.
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if ((Desc.TSFlags & X86II::Op0Mask) == X86II::XD) {
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MCE.emitByte(0xF2); MCE.emitByte(0x0F);
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}
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// Emit the double precision sse fp opcode prefix as needed.
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if ((Desc.TSFlags & X86II::Op0Mask) == X86II::XS) {
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MCE.emitByte(0xF3); MCE.emitByte(0x0F);
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}
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switch (Desc.TSFlags & X86II::Op0Mask) {
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case X86II::TB:
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MCE.emitByte(0x0F); // Two-byte opcode prefix
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break;
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case X86II::REP: break; // already handled.
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case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
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case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
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MCE.emitByte(0xD8+
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(((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
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>> X86II::Op0Shift));
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break; // Two-byte opcode prefix
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default: assert(0 && "Invalid prefix!");
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case 0: break; // No prefix!
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}
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unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
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switch (Desc.TSFlags & X86II::FormMask) {
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default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
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case X86II::Pseudo:
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if (Opcode != X86::IMPLICIT_USE &&
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Opcode != X86::IMPLICIT_DEF &&
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Opcode != X86::FP_REG_KILL)
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std::cerr << "X86 Machine Code Emitter: No 'form', not emitting: " << MI;
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break;
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case X86II::RawFrm:
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MCE.emitByte(BaseOpcode);
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if (MI.getNumOperands() == 1) {
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const MachineOperand &MO = MI.getOperand(0);
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if (MO.isMachineBasicBlock()) {
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emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
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} else if (MO.isGlobalAddress()) {
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assert(MO.isPCRelative() && "Call target is not PC Relative?");
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bool isTailCall = Opcode == X86::TAILJMPd ||
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Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
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emitGlobalAddressForCall(MO.getGlobal(), isTailCall);
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} else if (MO.isExternalSymbol()) {
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bool isTailCall = Opcode == X86::TAILJMPd ||
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Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
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emitExternalSymbolAddress(MO.getSymbolName(), true, isTailCall);
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} else if (MO.isImmediate()) {
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emitConstant(MO.getImmedValue(), sizeOfImm(Desc));
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} else {
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assert(0 && "Unknown RawFrm operand!");
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}
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}
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break;
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case X86II::AddRegFrm:
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MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
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if (MI.getNumOperands() == 2) {
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const MachineOperand &MO1 = MI.getOperand(1);
|
|
if (Value *V = MO1.getVRegValueOrNull()) {
|
|
assert(sizeOfImm(Desc) == 4 &&
|
|
"Don't know how to emit non-pointer values!");
|
|
emitGlobalAddressForPtr(cast<GlobalValue>(V));
|
|
} else if (MO1.isGlobalAddress()) {
|
|
assert(sizeOfImm(Desc) == 4 &&
|
|
"Don't know how to emit non-pointer values!");
|
|
assert(!MO1.isPCRelative() && "Function pointer ref is PC relative?");
|
|
emitGlobalAddressForPtr(MO1.getGlobal(), MO1.getOffset());
|
|
} else if (MO1.isExternalSymbol()) {
|
|
assert(sizeOfImm(Desc) == 4 &&
|
|
"Don't know how to emit non-pointer values!");
|
|
emitExternalSymbolAddress(MO1.getSymbolName(), false, false);
|
|
} else {
|
|
emitConstant(MO1.getImmedValue(), sizeOfImm(Desc));
|
|
}
|
|
}
|
|
break;
|
|
|
|
case X86II::MRMDestReg: {
|
|
MCE.emitByte(BaseOpcode);
|
|
emitRegModRMByte(MI.getOperand(0).getReg(),
|
|
getX86RegNum(MI.getOperand(1).getReg()));
|
|
if (MI.getNumOperands() == 3)
|
|
emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
|
|
break;
|
|
}
|
|
case X86II::MRMDestMem:
|
|
MCE.emitByte(BaseOpcode);
|
|
emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
|
|
if (MI.getNumOperands() == 6)
|
|
emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
|
|
break;
|
|
|
|
case X86II::MRMSrcReg:
|
|
MCE.emitByte(BaseOpcode);
|
|
|
|
emitRegModRMByte(MI.getOperand(1).getReg(),
|
|
getX86RegNum(MI.getOperand(0).getReg()));
|
|
if (MI.getNumOperands() == 3)
|
|
emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
|
|
break;
|
|
|
|
case X86II::MRMSrcMem:
|
|
MCE.emitByte(BaseOpcode);
|
|
emitMemModRMByte(MI, 1, getX86RegNum(MI.getOperand(0).getReg()));
|
|
if (MI.getNumOperands() == 2+4)
|
|
emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
|
|
break;
|
|
|
|
case X86II::MRM0r: case X86II::MRM1r:
|
|
case X86II::MRM2r: case X86II::MRM3r:
|
|
case X86II::MRM4r: case X86II::MRM5r:
|
|
case X86II::MRM6r: case X86II::MRM7r:
|
|
MCE.emitByte(BaseOpcode);
|
|
emitRegModRMByte(MI.getOperand(0).getReg(),
|
|
(Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
|
|
|
|
if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
|
|
emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(),
|
|
sizeOfImm(Desc));
|
|
}
|
|
break;
|
|
|
|
case X86II::MRM0m: case X86II::MRM1m:
|
|
case X86II::MRM2m: case X86II::MRM3m:
|
|
case X86II::MRM4m: case X86II::MRM5m:
|
|
case X86II::MRM6m: case X86II::MRM7m:
|
|
MCE.emitByte(BaseOpcode);
|
|
emitMemModRMByte(MI, 0, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);
|
|
|
|
if (MI.getNumOperands() == 5) {
|
|
if (MI.getOperand(4).isImmediate())
|
|
emitConstant(MI.getOperand(4).getImmedValue(), sizeOfImm(Desc));
|
|
else if (MI.getOperand(4).isGlobalAddress())
|
|
emitGlobalAddressForPtr(MI.getOperand(4).getGlobal(),
|
|
MI.getOperand(4).getOffset());
|
|
else
|
|
assert(0 && "Unknown operand!");
|
|
}
|
|
break;
|
|
}
|
|
}
|