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02170c0034
the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101840 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
2.6 KiB
LLVM
92 lines
2.6 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vld1i8(i8* %A) nounwind {
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;CHECK: vld1i8:
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;CHECK: vld1.8
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%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A)
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ret <8 x i8> %tmp1
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}
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define <4 x i16> @vld1i16(i16* %A) nounwind {
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;CHECK: vld1i16:
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;CHECK: vld1.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0)
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ret <4 x i16> %tmp1
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}
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define <2 x i32> @vld1i32(i32* %A) nounwind {
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;CHECK: vld1i32:
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;CHECK: vld1.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0)
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ret <2 x i32> %tmp1
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}
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define <2 x float> @vld1f(float* %A) nounwind {
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;CHECK: vld1f:
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;CHECK: vld1.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0)
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ret <2 x float> %tmp1
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}
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define <1 x i64> @vld1i64(i64* %A) nounwind {
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;CHECK: vld1i64:
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;CHECK: vld1.64
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0)
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ret <1 x i64> %tmp1
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}
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define <16 x i8> @vld1Qi8(i8* %A) nounwind {
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;CHECK: vld1Qi8:
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;CHECK: vld1.8
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%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A)
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ret <16 x i8> %tmp1
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}
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define <8 x i16> @vld1Qi16(i16* %A) nounwind {
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;CHECK: vld1Qi16:
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;CHECK: vld1.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0)
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ret <8 x i16> %tmp1
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}
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define <4 x i32> @vld1Qi32(i32* %A) nounwind {
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;CHECK: vld1Qi32:
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;CHECK: vld1.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0)
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ret <4 x i32> %tmp1
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}
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define <4 x float> @vld1Qf(float* %A) nounwind {
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;CHECK: vld1Qf:
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;CHECK: vld1.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0)
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ret <4 x float> %tmp1
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}
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define <2 x i64> @vld1Qi64(i64* %A) nounwind {
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;CHECK: vld1Qi64:
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;CHECK: vld1.64
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0)
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ret <2 x i64> %tmp1
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}
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declare <8 x i8> @llvm.arm.neon.vld1.v8i8(i8*) nounwind readonly
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declare <4 x i16> @llvm.arm.neon.vld1.v4i16(i8*) nounwind readonly
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declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*) nounwind readonly
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declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*) nounwind readonly
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declare <1 x i64> @llvm.arm.neon.vld1.v1i64(i8*) nounwind readonly
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declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8*) nounwind readonly
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declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*) nounwind readonly
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declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*) nounwind readonly
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declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
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declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly
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