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shim between the TargetTransformInfo immutable pass and the Subtarget via the TargetMachine and Function. Migrate a single call from BasicTargetTransformInfo as an example and provide shims where TargetMachine begins taking a Function to determine the subtarget. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218004 91177308-0d34-0410-b5e6-96231b3b80d8
422 lines
13 KiB
C++
422 lines
13 KiB
C++
//===-- PPCTargetTransformInfo.cpp - PPC specific TTI pass ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// PPC target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppctti"
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static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
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cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
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// Declare the pass initialization routine locally as target-specific passes
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// don't have a target-wide initialization entry point, and so we rely on the
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// pass constructor initialization.
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namespace llvm {
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void initializePPCTTIPass(PassRegistry &);
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}
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namespace {
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class PPCTTI final : public ImmutablePass, public TargetTransformInfo {
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const TargetMachine *TM;
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const PPCSubtarget *ST;
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const PPCTargetLowering *TLI;
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public:
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PPCTTI() : ImmutablePass(ID), ST(nullptr), TLI(nullptr) {
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llvm_unreachable("This pass cannot be directly constructed");
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}
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PPCTTI(const PPCTargetMachine *TM)
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: ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
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TLI(TM->getSubtargetImpl()->getTargetLowering()) {
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initializePPCTTIPass(*PassRegistry::getPassRegistry());
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}
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void initializePass() override {
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pushTTIStack(this);
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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TargetTransformInfo::getAnalysisUsage(AU);
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}
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/// Pass identification.
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static char ID;
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/// Provide necessary pointer adjustments for the two base classes.
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void *getAdjustedAnalysisPointer(const void *ID) override {
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if (ID == &TargetTransformInfo::ID)
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return (TargetTransformInfo*)this;
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return this;
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}
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/// \name Scalar TTI Implementations
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/// @{
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unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
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unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty) const override;
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unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty) const override;
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PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override;
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void getUnrollingPreferences(const Function *F, Loop *L,
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UnrollingPreferences &UP) const override;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool Vector) const override;
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unsigned getRegisterBitWidth(bool Vector) const override;
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unsigned getMaxInterleaveFactor() const override;
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unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind,
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OperandValueKind, OperandValueProperties,
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OperandValueProperties) const override;
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unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
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int Index, Type *SubTp) const override;
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unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const override;
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unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) const override;
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unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) const override;
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unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace) const override;
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/// @}
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};
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} // end anonymous namespace
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INITIALIZE_AG_PASS(PPCTTI, TargetTransformInfo, "ppctti",
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"PPC Target Transform Info", true, true, false)
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char PPCTTI::ID = 0;
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ImmutablePass *
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llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) {
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return new PPCTTI(TM);
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}
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//===----------------------------------------------------------------------===//
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//
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// PPC cost model.
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//
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//===----------------------------------------------------------------------===//
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PPCTTI::PopcntSupportKind PPCTTI::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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if (ST->hasPOPCNTD() && TyWidth <= 64)
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return PSK_FastHardware;
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return PSK_Software;
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}
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unsigned PPCTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
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if (DisablePPCConstHoist)
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return TargetTransformInfo::getIntImmCost(Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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if (Imm == 0)
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return TCC_Free;
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if (Imm.getBitWidth() <= 64) {
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if (isInt<16>(Imm.getSExtValue()))
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return TCC_Basic;
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if (isInt<32>(Imm.getSExtValue())) {
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// A constant that can be materialized using lis.
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if ((Imm.getZExtValue() & 0xFFFF) == 0)
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return TCC_Basic;
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return 2 * TCC_Basic;
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}
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}
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return 4 * TCC_Basic;
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}
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unsigned PPCTTI::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty) const {
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if (DisablePPCConstHoist)
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return TargetTransformInfo::getIntImmCost(IID, Idx, Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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switch (IID) {
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default: return TCC_Free;
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::usub_with_overflow:
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if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))
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return TCC_Free;
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break;
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}
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return PPCTTI::getIntImmCost(Imm, Ty);
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}
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unsigned PPCTTI::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty) const {
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if (DisablePPCConstHoist)
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return TargetTransformInfo::getIntImmCost(Opcode, Idx, Imm, Ty);
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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unsigned ImmIdx = ~0U;
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bool ShiftedFree = false, RunFree = false, UnsignedFree = false,
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ZeroFree = false;
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switch (Opcode) {
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default: return TCC_Free;
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case Instruction::GetElementPtr:
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// Always hoist the base address of a GetElementPtr. This prevents the
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// creation of new constants for every base constant that gets constant
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// folded with the offset.
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if (Idx == 0)
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return 2 * TCC_Basic;
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return TCC_Free;
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case Instruction::And:
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RunFree = true; // (for the rotate-and-mask instructions)
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// Fallthrough...
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case Instruction::Add:
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case Instruction::Or:
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case Instruction::Xor:
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ShiftedFree = true;
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// Fallthrough...
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case Instruction::Sub:
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case Instruction::Mul:
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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ImmIdx = 1;
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break;
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case Instruction::ICmp:
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UnsignedFree = true;
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ImmIdx = 1;
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// Fallthrough... (zero comparisons can use record-form instructions)
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case Instruction::Select:
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ZeroFree = true;
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break;
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case Instruction::PHI:
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case Instruction::Call:
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case Instruction::Ret:
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case Instruction::Load:
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case Instruction::Store:
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break;
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}
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if (ZeroFree && Imm == 0)
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return TCC_Free;
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if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {
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if (isInt<16>(Imm.getSExtValue()))
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return TCC_Free;
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if (RunFree) {
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if (Imm.getBitWidth() <= 32 &&
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(isShiftedMask_32(Imm.getZExtValue()) ||
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isShiftedMask_32(~Imm.getZExtValue())))
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return TCC_Free;
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if (ST->isPPC64() &&
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(isShiftedMask_64(Imm.getZExtValue()) ||
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isShiftedMask_64(~Imm.getZExtValue())))
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return TCC_Free;
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}
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if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))
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return TCC_Free;
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if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)
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return TCC_Free;
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}
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return PPCTTI::getIntImmCost(Imm, Ty);
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}
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void PPCTTI::getUnrollingPreferences(const Function *F, Loop *L,
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UnrollingPreferences &UP) const {
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if (TM->getSubtarget<PPCSubtarget>(F).getDarwinDirective() == PPC::DIR_A2) {
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// The A2 is in-order with a deep pipeline, and concatenation unrolling
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// helps expose latency-hiding opportunities to the instruction scheduler.
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UP.Partial = UP.Runtime = true;
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}
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}
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unsigned PPCTTI::getNumberOfRegisters(bool Vector) const {
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if (Vector && !ST->hasAltivec())
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return 0;
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return ST->hasVSX() ? 64 : 32;
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}
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unsigned PPCTTI::getRegisterBitWidth(bool Vector) const {
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if (Vector) {
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if (ST->hasAltivec()) return 128;
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return 0;
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}
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if (ST->isPPC64())
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return 64;
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return 32;
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}
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unsigned PPCTTI::getMaxInterleaveFactor() const {
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unsigned Directive = ST->getDarwinDirective();
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// The 440 has no SIMD support, but floating-point instructions
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// have a 5-cycle latency, so unroll by 5x for latency hiding.
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if (Directive == PPC::DIR_440)
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return 5;
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// The A2 has no SIMD support, but floating-point instructions
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// have a 6-cycle latency, so unroll by 6x for latency hiding.
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if (Directive == PPC::DIR_A2)
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return 6;
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// FIXME: For lack of any better information, do no harm...
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if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
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return 1;
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// For most things, modern systems have two execution units (and
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// out-of-order execution).
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return 2;
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}
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unsigned PPCTTI::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, OperandValueKind Op1Info,
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OperandValueKind Op2Info, OperandValueProperties Opd1PropInfo,
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OperandValueProperties Opd2PropInfo) const {
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assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
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// Fallback to the default implementation.
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return TargetTransformInfo::getArithmeticInstrCost(
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Opcode, Ty, Op1Info, Op2Info, Opd1PropInfo, Opd2PropInfo);
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}
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unsigned PPCTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp) const {
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return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
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}
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unsigned PPCTTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
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assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
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return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
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}
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unsigned PPCTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) const {
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return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
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}
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unsigned PPCTTI::getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) const {
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assert(Val->isVectorTy() && "This must be a vector type");
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
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// Double-precision scalars are already located in index #0.
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if (Index == 0)
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return 0;
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return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
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}
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// Estimated cost of a load-hit-store delay. This was obtained
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// experimentally as a minimum needed to prevent unprofitable
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// vectorization for the paq8p benchmark. It may need to be
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// raised further if other unprofitable cases remain.
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unsigned LHSPenalty = 2;
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if (ISD == ISD::INSERT_VECTOR_ELT)
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LHSPenalty += 7;
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// Vector element insert/extract with Altivec is very expensive,
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// because they require store and reload with the attendant
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// processor stall for load-hit-store. Until VSX is available,
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// these need to be estimated as very costly.
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if (ISD == ISD::EXTRACT_VECTOR_ELT ||
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ISD == ISD::INSERT_VECTOR_ELT)
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return LHSPenalty +
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TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
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return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
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}
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unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace) const {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
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assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
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"Invalid Opcode");
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unsigned Cost =
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TargetTransformInfo::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
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// VSX loads/stores support unaligned access.
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if (ST->hasVSX()) {
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if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64)
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return Cost;
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}
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bool UnalignedAltivec =
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Src->isVectorTy() &&
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Src->getPrimitiveSizeInBits() >= LT.second.getSizeInBits() &&
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LT.second.getSizeInBits() == 128 &&
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Opcode == Instruction::Load;
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// PPC in general does not support unaligned loads and stores. They'll need
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// to be decomposed based on the alignment factor.
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unsigned SrcBytes = LT.second.getStoreSize();
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if (SrcBytes && Alignment && Alignment < SrcBytes && !UnalignedAltivec) {
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Cost += LT.first*(SrcBytes/Alignment-1);
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// For a vector type, there is also scalarization overhead (only for
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// stores, loads are expanded using the vector-load + permutation sequence,
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// which is much less expensive).
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if (Src->isVectorTy() && Opcode == Instruction::Store)
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for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
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Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);
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}
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return Cost;
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}
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