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https://github.com/c64scene-ar/llvm-6502.git
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fb6fe0aea2
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179500 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.5 KiB
LLVM
54 lines
1.5 KiB
LLVM
; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64
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declare void @foo()
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define i32 @test_cr2() nounwind {
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entry:
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%ret = alloca i32, align 4
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%0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
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store i32 %0, i32* %ret, align 4
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call void @foo()
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%1 = load i32* %ret, align 4
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ret i32 %1
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}
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; PPC32: mfcr 12
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; PPC32-NEXT: stw 12, {{[0-9]+}}(31)
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; PPC32: lwz 12, {{[0-9]+}}(31)
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; PPC32-NEXT: mtcrf 32, 12
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; PPC64: mfcr 12
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; PPC64: stw 12, 8(1)
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; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
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; PPC64: addi 1, 1, [[AMT]]
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; PPC64: lwz 12, 8(1)
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; PPC64: mtcrf 32, 12
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define i32 @test_cr234() nounwind {
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entry:
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%ret = alloca i32, align 4
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%0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09cmp 3,$2,$2\0A\09cmp 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind
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store i32 %0, i32* %ret, align 4
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call void @foo()
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%1 = load i32* %ret, align 4
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ret i32 %1
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}
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; PPC32: mfcr 12
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; PPC32-NEXT: stw 12, {{[0-9]+}}(31)
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; PPC32: lwz 12, {{[0-9]+}}(31)
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; PPC32-NEXT: mtcrf 32, 12
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; PPC32-NEXT: mtcrf 16, 12
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; PPC32-NEXT: mtcrf 8, 12
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; PPC64: mfcr 12
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; PPC64: stw 12, 8(1)
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; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
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; PPC64: addi 1, 1, [[AMT]]
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; PPC64: lwz 12, 8(1)
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; PPC64: mtcrf 32, 12
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; PPC64: mtcrf 16, 12
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; PPC64: mtcrf 8, 12
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