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https://github.com/c64scene-ar/llvm-6502.git
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1fd36e41e4
form of call in preference to memory indirect on Atom. In this case, the patch applies the optimization to the code for reloading spilled registers. The patch also includes changes to sibcall.ll and movgs.ll, which were failing on the Atom buildbot after the first patch was applied. This patch by Sriram Murali. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178193 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
2.3 KiB
LLVM
75 lines
2.3 KiB
LLVM
; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=sse41 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn -mattr=sse41 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=penryn -mattr=sse41 | FileCheck %s --check-prefix=X64
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define i32 @test1() nounwind readonly {
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entry:
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%tmp = load i32* addrspace(256)* getelementptr (i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; <i32*> [#uses=1]
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%tmp1 = load i32* %tmp ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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; X32: test1:
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; X32: movl %gs:196, %eax
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; X32: movl (%eax), %eax
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; X32: ret
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; X64: test1:
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; X64: movq %gs:320, %rax
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; X64: movl (%rax), %eax
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; X64: ret
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define i64 @test2(void (i8*)* addrspace(256)* %tmp8) nounwind {
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entry:
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%tmp9 = load void (i8*)* addrspace(256)* %tmp8, align 8
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tail call void %tmp9(i8* undef) nounwind optsize
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ret i64 0
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}
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; rdar://8453210
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; X32: test2:
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; X32: movl {{.*}}(%esp), %eax
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; X32: calll *%gs:(%eax)
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; X64: test2:
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; X64: callq *%gs:([[A0:%rdi|%rcx]])
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define <2 x i64> @pmovsxwd_1(i64 addrspace(256)* %p) nounwind readonly {
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entry:
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%0 = load i64 addrspace(256)* %p
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%tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0
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%1 = bitcast <2 x i64> %tmp2 to <8 x i16>
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%2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone
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%3 = bitcast <4 x i32> %2 to <2 x i64>
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ret <2 x i64> %3
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; X32: pmovsxwd_1:
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; X32: movl 4(%esp), %eax
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; X32: pmovsxwd %gs:(%eax), %xmm0
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; X32: ret
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; X64: pmovsxwd_1:
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; X64: pmovsxwd %gs:([[A0]]), %xmm0
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; X64: ret
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}
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; The two loads here both look identical to selection DAG, except for their
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; address spaces. Make sure they aren't CSE'd.
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define i32 @test_no_cse() nounwind readonly {
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entry:
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%tmp = load i32* addrspace(256)* getelementptr (i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; <i32*> [#uses=1]
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%tmp1 = load i32* %tmp ; <i32> [#uses=1]
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%tmp2 = load i32* addrspace(257)* getelementptr (i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1]
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%tmp3 = load i32* %tmp2 ; <i32> [#uses=1]
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%tmp4 = add i32 %tmp1, %tmp3
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ret i32 %tmp4
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}
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; X32: test_no_cse:
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; X32: movl %gs:196
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; X32: movl %fs:196
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; X32: ret
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
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