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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122398 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
4.1 KiB
C++
140 lines
4.1 KiB
C++
//===-- PTXISelDAGToDAG.cpp - A dag to dag inst selector for PTX ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the PTX target.
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//
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//===----------------------------------------------------------------------===//
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#include "PTX.h"
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#include "PTXTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/DerivedTypes.h"
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using namespace llvm;
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namespace {
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// PTXDAGToDAGISel - PTX specific code to select PTX machine
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// instructions for SelectionDAG operations.
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class PTXDAGToDAGISel : public SelectionDAGISel {
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public:
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PTXDAGToDAGISel(PTXTargetMachine &TM, CodeGenOpt::Level OptLevel);
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virtual const char *getPassName() const {
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return "PTX DAG->DAG Pattern Instruction Selection";
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}
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SDNode *Select(SDNode *Node);
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDValue &Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRii(SDValue &Addr, SDValue &Base, SDValue &Offset);
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// Include the pieces auto'gened from the target description
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#include "PTXGenDAGISel.inc"
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private:
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bool isImm(const SDValue &operand);
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bool SelectImm(const SDValue &operand, SDValue &imm);
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}; // class PTXDAGToDAGISel
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} // namespace
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// createPTXISelDag - This pass converts a legalized DAG into a
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// PTX-specific DAG, ready for instruction scheduling
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FunctionPass *llvm::createPTXISelDag(PTXTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new PTXDAGToDAGISel(TM, OptLevel);
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}
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PTXDAGToDAGISel::PTXDAGToDAGISel(PTXTargetMachine &TM,
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CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel) {}
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SDNode *PTXDAGToDAGISel::Select(SDNode *Node) {
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// SelectCode() is auto'gened
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return SelectCode(Node);
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}
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// Match memory operand of the form [reg+reg]
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bool PTXDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2) {
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if (Addr.getOpcode() != ISD::ADD || Addr.getNumOperands() < 2 ||
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isImm(Addr.getOperand(0)) || isImm(Addr.getOperand(1)))
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return false;
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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return true;
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}
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// Match memory operand of the form [reg], [imm+reg], and [reg+imm]
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bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
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SDValue &Offset) {
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if (Addr.getOpcode() != ISD::ADD) {
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if (isImm(Addr))
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return false;
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// is [reg] but not [imm]
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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// let SelectADDRii handle the [imm+imm] case
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if (Addr.getNumOperands() >= 2 &&
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isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1)))
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return false;
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// try [reg+imm] and [imm+reg]
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for (int i = 0; i < 2; i ++)
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if (SelectImm(Addr.getOperand(1-i), Offset)) {
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Base = Addr.getOperand(i);
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return true;
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}
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// either [reg+imm] and [imm+reg]
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for (int i = 0; i < 2; i ++)
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if (SelectImm(Addr.getOperand(1-i), Offset)) {
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Base = Addr.getOperand(i);
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return true;
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}
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return false;
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}
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// Match memory operand of the form [imm+imm] and [imm]
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bool PTXDAGToDAGISel::SelectADDRii(SDValue &Addr, SDValue &Base,
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SDValue &Offset) {
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// is [imm+imm]?
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if (Addr.getOpcode() == ISD::ADD) {
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return SelectImm(Addr.getOperand(0), Base) &&
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SelectImm(Addr.getOperand(1), Offset);
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}
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// is [imm]?
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if (SelectImm(Addr, Base)) {
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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return false;
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}
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bool PTXDAGToDAGISel::isImm(const SDValue &operand) {
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return ConstantSDNode::classof(operand.getNode());
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}
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bool PTXDAGToDAGISel::SelectImm(const SDValue &operand, SDValue &imm) {
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SDNode *node = operand.getNode();
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if (!ConstantSDNode::classof(node))
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return false;
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ConstantSDNode *CN = cast<ConstantSDNode>(node);
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imm = CurDAG->getTargetConstant(*CN->getConstantIntValue(), MVT::i32);
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return true;
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}
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