mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2ef9c8a43d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89328 91177308-0d34-0410-b5e6-96231b3b80d8
359 lines
11 KiB
C++
359 lines
11 KiB
C++
//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an ARM MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "ARM.h" // FIXME: FACTOR ENUMS BETTER.
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#include "ARMInstPrinter.h"
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#include "ARMAddressingModes.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Include the auto-generated portion of the assembly writer.
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#define MachineInstr MCInst
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#define ARMAsmPrinter ARMInstPrinter // FIXME: REMOVE.
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#define NO_ASM_WRITER_BOILERPLATE
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#include "ARMGenAsmWriter.inc"
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#undef MachineInstr
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#undef ARMAsmPrinter
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void ARMInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
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void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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const char *Modifier) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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unsigned Reg = Op.getReg();
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if (Modifier && strcmp(Modifier, "dregpair") == 0) {
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// FIXME: Breaks e.g. ARM/vmul.ll.
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assert(0);
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/*
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unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
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unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
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O << '{'
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<< getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
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<< '}';*/
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} else if (Modifier && strcmp(Modifier, "lane") == 0) {
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assert(0);
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/*
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unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
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unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
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&ARM::DPR_VFP2RegClass);
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O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
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*/
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} else {
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O << getRegisterName(Reg);
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}
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} else if (Op.isImm()) {
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assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
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O << '#' << Op.getImm();
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} else {
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assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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Op.getExpr()->print(O, &MAI);
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}
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}
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static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
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const MCAsmInfo *MAI) {
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// Break it up into two parts that make up a shifter immediate.
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V = ARM_AM::getSOImmVal(V);
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assert(V != -1 && "Not a valid so_imm value!");
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unsigned Imm = ARM_AM::getSOImmValImm(V);
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unsigned Rot = ARM_AM::getSOImmValRot(V);
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// Print low-level immediate formation info, per
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// A5.1.3: "Data-processing operands - Immediate".
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if (Rot) {
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O << "#" << Imm << ", " << Rot;
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// Pretty printed version.
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if (VerboseAsm)
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O << ' ' << MAI->getCommentString()
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<< ' ' << (int)ARM_AM::rotr32(Imm, Rot);
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} else {
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O << "#" << Imm;
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}
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}
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/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
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/// immediate in bits 0-7.
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void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) {
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const MCOperand &MO = MI->getOperand(OpNum);
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assert(MO.isImm() && "Not a valid so_imm value!");
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printSOImm(O, MO.getImm(), VerboseAsm, &MAI);
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}
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/// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
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/// followed by an 'orr' to materialize.
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void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) {
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// FIXME: REMOVE this method.
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abort();
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}
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// so_reg is a 4-operand unit corresponding to register forms of the A5.1
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// "Addressing Mode 1 - Data-processing operands" forms. This includes:
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// REG 0 0 - e.g. R5
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// REG REG 0,SH_OPC - e.g. R5, ROR R3
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// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
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void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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const MCOperand &MO3 = MI->getOperand(OpNum+2);
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O << getRegisterName(MO1.getReg());
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// Print the shift opc.
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
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<< ' ';
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if (MO2.getReg()) {
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O << getRegisterName(MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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} else {
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O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
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}
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}
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void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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const MCOperand &MO3 = MI->getOperand(Op+2);
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if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, Op);
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return;
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}
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O << "[" << getRegisterName(MO1.getReg());
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if (!MO2.getReg()) {
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if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
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O << ", #"
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<< (char)ARM_AM::getAM2Op(MO3.getImm())
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<< ARM_AM::getAM2Offset(MO3.getImm());
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O << "]";
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return;
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}
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O << ", "
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<< (char)ARM_AM::getAM2Op(MO3.getImm())
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<< getRegisterName(MO2.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
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<< " #" << ShImm;
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O << "]";
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}
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void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
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unsigned OpNum) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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if (!MO1.getReg()) {
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unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
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assert(ImmOffs && "Malformed indexed load / store!");
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O << '#' << (char)ARM_AM::getAM2Op(MO2.getImm()) << ImmOffs;
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return;
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}
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O << (char)ARM_AM::getAM2Op(MO2.getImm()) << getRegisterName(MO1.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
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<< " #" << ShImm;
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}
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void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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const MCOperand &MO3 = MI->getOperand(OpNum+2);
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O << '[' << getRegisterName(MO1.getReg());
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if (MO2.getReg()) {
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O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
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<< getRegisterName(MO2.getReg()) << ']';
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return;
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}
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if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
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O << ", #"
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<< (char)ARM_AM::getAM3Op(MO3.getImm())
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<< ImmOffs;
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O << ']';
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}
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void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
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unsigned OpNum) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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if (MO1.getReg()) {
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O << (char)ARM_AM::getAM3Op(MO2.getImm())
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<< getRegisterName(MO1.getReg());
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return;
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}
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unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
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assert(ImmOffs && "Malformed indexed load / store!");
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O << "#"
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<< (char)ARM_AM::getAM3Op(MO2.getImm())
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<< ImmOffs;
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}
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void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
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const char *Modifier) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
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if (Modifier && strcmp(Modifier, "submode") == 0) {
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if (MO1.getReg() == ARM::SP) {
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// FIXME
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bool isLDM = (MI->getOpcode() == ARM::LDM ||
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MI->getOpcode() == ARM::LDM_RET ||
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MI->getOpcode() == ARM::t2LDM ||
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MI->getOpcode() == ARM::t2LDM_RET);
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O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
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} else
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O << ARM_AM::getAMSubModeStr(Mode);
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} else if (Modifier && strcmp(Modifier, "wide") == 0) {
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ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
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if (Mode == ARM_AM::ia)
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O << ".w";
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} else {
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printOperand(MI, OpNum);
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if (ARM_AM::getAM4WBFlag(MO2.getImm()))
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O << "!";
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}
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}
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void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
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const char *Modifier) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, OpNum);
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return;
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}
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if (Modifier && strcmp(Modifier, "submode") == 0) {
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ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
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O << ARM_AM::getAMSubModeStr(Mode);
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return;
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} else if (Modifier && strcmp(Modifier, "base") == 0) {
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// Used for FSTM{D|S} and LSTM{D|S} operations.
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O << getRegisterName(MO1.getReg());
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if (ARM_AM::getAM5WBFlag(MO2.getImm()))
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O << "!";
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return;
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}
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O << "[" << getRegisterName(MO1.getReg());
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if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
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O << ", #"
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<< (char)ARM_AM::getAM5Op(MO2.getImm())
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<< ImmOffs*4;
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}
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O << "]";
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}
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void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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const MCOperand &MO3 = MI->getOperand(OpNum+2);
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// FIXME: No support yet for specifying alignment.
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O << '[' << getRegisterName(MO1.getReg()) << ']';
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if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
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if (MO2.getReg() == 0)
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O << '!';
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else
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O << ", " << getRegisterName(MO2.getReg());
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}
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}
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void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
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const char *Modifier) {
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assert(0 && "FIXME: Implement printAddrModePCOperand");
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}
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void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI,
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unsigned OpNum) {
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const MCOperand &MO = MI->getOperand(OpNum);
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uint32_t v = ~MO.getImm();
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int32_t lsb = CountTrailingZeros_32(v);
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int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
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assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
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O << '#' << lsb << ", #" << width;
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}
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void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) {
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O << "{";
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// Always skip the first operand, it's the optional (and implicit writeback).
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for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
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if (i != OpNum+1) O << ", ";
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O << getRegisterName(MI->getOperand(i).getReg());
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}
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O << "}";
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}
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void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum) {
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ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
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if (CC != ARMCC::AL)
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O << ARMCondCodeToString(CC);
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}
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void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum){
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if (MI->getOperand(OpNum).getReg()) {
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assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
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"Expect ARM CPSR register!");
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O << 's';
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}
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}
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void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
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const char *Modifier) {
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// FIXME: remove this.
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abort();
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}
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void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum) {
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O << MI->getOperand(OpNum).getImm();
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}
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void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum) {
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// FIXME: remove this.
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abort();
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}
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void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum) {
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// FIXME: remove this.
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abort();
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}
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